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1. 发明授权

US08318518B2 Light emitting device and manufacturing method thereof 有权
标题翻译：发光元件及其制造方法
公开(公告)号：US08318518B2
公开(公告)日：2012-11-27
申请号：US12952489
申请日：2010-11-23
申请人： Hitoshi Hoshino , Toshiyuki Tateishi
发明人： Hitoshi Hoshino , Toshiyuki Tateishi
IPC分类号： H01L21/00
CPC分类号： H01L33/20 , H01L33/007
摘要： A light emitting device including a sapphire layer and a light emitting layer formed on the sapphire layer. The sapphire layer has a polygonal sectional shape whose internal angle is an obtuse angle, such as a regular hexagonal shape. Light emitted from the light emitting layer is totally reflected on one side surface of the sapphire layer and next transmitted through another side surface of the sapphire layer.
摘要翻译：一种发光器件，包括形成在蓝宝石层上的蓝宝石层和发光层。蓝宝石层具有内角为正六边形的钝角的多边形截面形状。从发光层发射的光在蓝宝石层的一个侧表面上被全反射，然后透过蓝宝石层的另一侧表面。

2. 发明申请

US20110133235A1 LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：发光装置及其制造方法
公开(公告)号：US20110133235A1
公开(公告)日：2011-06-09
申请号：US12952489
申请日：2010-11-23
申请人： Hitoshi Hoshino , Toshiyuki Tateishi
发明人： Hitoshi Hoshino , Toshiyuki Tateishi
IPC分类号： H01L33/58 , H01L33/00
CPC分类号： H01L33/20 , H01L33/007
摘要： A light emitting device including a sapphire layer and a light emitting layer formed on the sapphire layer. The sapphire layer has a polygonal sectional shape whose internal angle is an obtuse angle, such as a regular hexagonal shape. Light emitted from the light emitting layer is totally reflected on one side surface of the sapphire layer and next transmitted through another side surface of the sapphire layer.
摘要翻译：一种发光器件，包括形成在蓝宝石层上的蓝宝石层和发光层。蓝宝石层具有内角为正六边形的钝角的多边形截面形状。从发光层发射的光在蓝宝石层的一个侧表面上被全反射，然后透过蓝宝石层的另一侧表面。

3. 发明申请

US20050259459A1 Wafer dividing method 有权
标题翻译：晶圆分割法
公开(公告)号：US20050259459A1
公开(公告)日：2005-11-24
申请号：US11128197
申请日：2005-05-13
申请人： Yusuke Nagai , Toshiyuki Tateishi , Tadato Nagasawa
发明人： Yusuke Nagai , Toshiyuki Tateishi , Tadato Nagasawa
IPC分类号： B23K26/00 , B23K26/40 , B23K101/40 , B28D5/00 , G11C5/06 , H01L21/301 , H01L21/68 , H01L21/78
CPC分类号： H01L21/78 , B23K26/40 , B23K26/53 , B23K2101/40 , B23K2103/50 , B28D5/0011 , H01L21/6835 , H01L21/6836 , H01L2221/68327 , H01L2221/68336 , Y10T225/12
摘要： A method of dividing a wafer having a plurality of first dividing lines and a plurality of second dividing lines intersecting with the first dividing lines formed on the surface of the wafer along the first dividing lines and the second dividing lines, which comprises an internal deteriorated layer forming step for forming a deteriorated layer in the inside of the water along the first dividing lines and the second dividing lines by applying a laser beam along the first dividing lines and the second dividing lines; an intersection deteriorated layer forming step for forming a deteriorated layer thicker than the deteriorated layer formed in the internal deteriorated layer forming step by applying a laser beam to intersection areas between the first dividing lines and the second dividing lines; and a dividing step for dividing the wafer into individual chips along the first dividing lines and the second dividing lines by exerting external force to the wafer.
摘要翻译：一种分割具有多个第一分割线和多条第二分割线的晶片的方法，该晶片具有与形成在晶片表面上的第一分割线相交的第一分割线和第二分割线，该第一分割线包括内部劣化层通过沿着第一分割线和第二分割线施加激光束，沿着第一分割线和第二分割线在水的内部形成劣化层的形成步骤; 交叉劣化层形成步骤，用于通过对第一分割线和第二分割线之间的交叉区域施加激光来形成比内部劣化层形成步骤中形成的劣化层更厚的劣化层; 以及分割步骤，通过向晶片施加外力，将晶片沿着第一分割线和第二分割线分割成单独的芯片。

4. 发明授权

US06498075B1 Dicing method 有权
标题翻译：切片方法
公开(公告)号：US06498075B1
公开(公告)日：2002-12-24
申请号：US09660261
申请日：2000-09-12
申请人： Kouji Fujimoto , Toshiyuki Tateishi
发明人： Kouji Fujimoto , Toshiyuki Tateishi
IPC分类号： H01L2146
CPC分类号： B28D5/024 , B28D5/023 , H01L21/3043 , H01L21/78
摘要： The present invention is to provide a dicing method of cutting a workpiece along the first streets and the second streets by using a cutting blade having an annular cutting edge provided on the outer peripheral portion on one side surface of a base plate, the workpiece having plural first streets and second streets intersected each other at a predetermined angle. When the second streets are to be cut after the first streets are cut, the cutting blade is so positioned that the side of the base plate faces the side of the unworked region of the workpiece.
摘要翻译：本发明提供一种通过使用具有设置在基板的一个侧面的外周部上的具有环形切削刃的切割刀沿着第一街道和第二街道切割工件的切割方法，所述工件具有多个第一街道和第二街道以预定角度彼此相交。当在第一街道被切割后要切割第二条街道时，切割刀片被定位成使得基板的侧面面向工件的未加工区域的一侧。

5. 发明申请

US20100261309A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20100261309A1
公开(公告)日：2010-10-14
申请号：US12722762
申请日：2010-03-12
申请人： Toshiyuki Tateishi
发明人： Toshiyuki Tateishi
IPC分类号： H01L21/56
CPC分类号： H01L21/56 , H01L21/561 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/97 , H01L2225/06506 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： A method of manufacturing a semiconductor device in which a second semiconductor chip is bonded to a surface of a first semiconductor chip. The method includes: a back side grinding step for grinding the back side of a wafer including a device area where a plurality of first semiconductor chips are formed, the grinding applied to an area corresponding to the device area, so as to reduce the thickness of the wafer in the device area to a predetermined finished thickness; a chip bonding step for bonding the second semiconductor chip to a predetermined position of the surface of each of the first semiconductor chips formed on the face-side surface of the wafer; and a wafer dividing step for dividing the wafer along streets to separate the device area of the wafer into individual semiconductor devices in each of which the second semiconductor chip is bonded to the surface of the first semiconductor chip.
摘要翻译：一种半导体器件的制造方法，其中第二半导体芯片接合到第一半导体芯片的表面。该方法包括：背面研磨步骤，用于研磨包括形成多个第一半导体芯片的器件区域的晶片的背面，所述研磨施加到与所述器件区域相对应的区域，以便减小所述装置区域中的所述晶片达到预定的最终厚度; 用于将第二半导体芯片接合到形成在晶片的表面侧表面上的每个第一半导体芯片的表面的预定位置的芯片接合步骤; 以及晶片划分步骤，用于沿着街道划分晶片以将晶片的器件区域分离为单独的半导体器件，其中第二半导体芯片被结合到第一半导体芯片的表面。

6. 发明授权

US06448151B2 Process for producing a large number of semiconductor chips from a semiconductor wafer 有权
标题翻译：用于从半导体晶片制造大量半导体芯片的工艺
公开(公告)号：US06448151B2
公开(公告)日：2002-09-10
申请号：US09817248
申请日：2001-03-27
申请人： Toshiyuki Tateishi
发明人： Toshiyuki Tateishi
IPC分类号： H01L2130
CPC分类号： H01L21/78 , B28D5/022 , Y10S438/977
摘要： A process for producing a large number of semiconductor chips from a semiconductor wafer having a large number of rectangular areas defined by streets arranged on the front surface in a lattice form, semiconductor circuits being formed in the respective rectangular areas. This process comprises the steps of forming a plurality of grooves having a predetermined depth in the back surface of the semiconductor wafer, grinding the back surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer to a predetermined value and thereafter, cutting the semiconductor wafer along the streets to separate the rectangular areas from one another to obtain semiconductor chips.
摘要翻译：一种用于从具有大量矩形区域的半导体晶片制造大量半导体芯片的方法，该矩形区域以格子形式布置在前表面上的街道，半导体电路形成在各个矩形区域中。该方法包括以下步骤：在半导体晶片的背表面中形成具有预定深度的多个凹槽，研磨半导体晶片的背面以将半导体晶片的厚度减小到预定值，之后切割半导体晶片沿着街道将矩形区域彼此分离以获得半导体芯片。

7. 发明授权

US07549560B2 Wafer dividing method 有权
标题翻译：晶圆分割法
公开(公告)号：US07549560B2
公开(公告)日：2009-06-23
申请号：US11128197
申请日：2005-05-13
申请人： Yusuke Nagai , Toshiyuki Tateishi , Tadato Nagasawa
发明人： Yusuke Nagai , Toshiyuki Tateishi , Tadato Nagasawa
IPC分类号： B26F3/00 , H01L21/66 , H01L21/20 , B23K26/38
CPC分类号： H01L21/78 , B23K26/40 , B23K26/53 , B23K2101/40 , B23K2103/50 , B28D5/0011 , H01L21/6835 , H01L21/6836 , H01L2221/68327 , H01L2221/68336 , Y10T225/12
摘要： A method of dividing a wafer along a plurality of first dividing lines and a plurality of second dividing lines intersecting with the first dividing lines on the surface of the wafer. The method includes an internal deteriorated layer forming step for forming a deteriorated layer in the inside of the wafer along both the first dividing lines and the second dividing lines by applying a laser beam along the first dividing lines and the second dividing lines. It also includes an intersection deteriorated layer forming step for forming a deteriorated layer thicker than the deteriorated layer formed in the internal deteriorated layer forming step by applying a laser beam to intersection areas between the first and second dividing lines. Thereafter, a dividing step divides the wafer into individual chips along the first and second dividing lines by exertion of external force to the wafer.
摘要翻译：在晶片的表面上沿多个第一分割线和与第一分割线交叉的多个第二分割线分割晶片的方法。该方法包括：通过沿着第一分割线和第二分割线施加激光束，沿着第一分割线和第二分割线在晶片内部形成劣化层的内部劣化层形成步骤。还包括用于通过对第一分割线和第二分割线之间的交叉区域施加激光来形成比内部劣化层形成步骤中形成的劣化层更厚的劣化层的交叉劣化层形成步骤。此后，分割步骤通过向晶片施加外力而沿着第一和第二分割线将晶片分成单独的芯片。

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