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1. 发明专利

JP2013257746A Input-output unit and control system 有权
标题翻译：输入输出单元和控制系统
公开(公告)号：JP2013257746A
公开(公告)日：2013-12-26
申请号：JP2012133558
申请日：2012-06-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ONOZUKA AKIHIRO , SHIMIZU TOSHIKI , UEMURA KAZUNORI , SHIRAISHI MASAHIRO
IPC分类号： G05B9/03 , H04Q9/00
摘要： PROBLEM TO BE SOLVED: To provide an input-output unit capable of specifying a circuit abnormal place.SOLUTION: The input-output unit includes an input-output device, a first conversion device, a second conversion device, a third conversion device, and a fourth conversion device. The first conversion device superposes a state response frame including a reception state of an optical signal on an electric signal to be sent to a control device, the second conversion device converts the electric signal with the state response frame transmitted by the first conversion device superposed thereon into an optical signal, the fourth conversion device superposes the state response frame including the reception state of the optical signal on an electric signal to be sent to the control device, and the third conversion device converts the electric signal with the state response frame transmitted by the fourth conversion device superposed thereon into an optical signal, acquires a reception state of the first conversion device from the first conversion device, superposes a state response frame including the reception state of the first conversion device on the optical signal to be sent to the control device in response to a state request frame from the control device.
摘要翻译：要解决的问题：提供能够指定电路异常位置的输入输出单元。解决方案：输入 - 输出单元包括输入输出设备，第一转换设备，第二转换设备，第三转换设备和第四转换装置。第一转换装置将包含光信号的接收状态的状态响应帧叠加在要发送给控制装置的电信号上，第二转换装置用由其上叠加的第一转换装置发送的状态响应帧转换电信号第四转换装置将包含光信号的接收状态的状态响应帧叠加在要发送给控制装置的电信号上，第三转换装置将电信号转换为由将其叠加在光信号中的第四转换装置从第一转换装置获取第一转换装置的接收状态，将包含第一转换装置的接收状态的状态响应帧叠加在要发送给控制的光信号上响应于来自控制设备的状态请求帧的设备。

2. 发明专利

JP2013110586A Communication system, communication device, and communication method 有权
标题翻译：通信系统，通信设备和通信方法
公开(公告)号：JP2013110586A
公开(公告)日：2013-06-06
申请号：JP2011254041
申请日：2011-11-21
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NISHIKAWA SATOSHI , NISHIMURA TAKAMASA , SHIMIZU KATSUTO , SHIRAISHI MASAHIRO , OTANI TATSUYUKI
IPC分类号： H04L12/46 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To reduce the processing load of reception data on a CPU by only making network superordinate software of the CPU controlling a communication device process data necessary for its own device.SOLUTION: A communication device having received a transmission frame from another communication device determines whether or not the communication device should perform reception processing of the received frame by getting a reception frame discard determination means 439 to compare a destination IP address and destination port number as a destination number which is the information included in the received frame with a destination IP address and destination port number indicating whether or not the communication device may perform reception processing stored in a storage device in the communication device. A LAN controller driver 421 will perform discard processing of the frame if the received frame is not a frame of which the communication device should perform reception processing, and network superordinate software 411 will perform frame reception processing if the received frame is a frame of which the communication device should perform reception processing.
摘要翻译：要解决的问题：通过仅使CPU的网络上级软件控制通信设备处理其自身设备所需的数据，来减少CPU上接收数据的处理负担。解决方案：从另一通信设备接收到传输帧的通信设备通过获取接收帧丢弃确定装置439来比较目的地IP地址和目的端口来确定通信设备是否应该对接收到的帧进行接收处理号码作为目的地号码，其是包括在具有目的地IP地址的接收帧中的信息和指示通信设备是否可以执行存储在通信设备中的存储设备中的接收处理的目的地端口号。如果接收到的帧不是通信设备应该执行接收处理的帧，则LAN控制器驱动器421将执行该帧的丢弃处理，并且如果接收的帧是其中的一个帧，则网络上级软件411将执行帧接收处理通信设备应进行接收处理。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012235335A Method and device for detecting incorrect connection between devices 审中-公开
标题翻译：用于检测设备之间不正确连接的方法和设备
公开(公告)号：JP2012235335A
公开(公告)日：2012-11-29
申请号：JP2011102967
申请日：2011-05-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAHARA YUKIKO , SHIRAISHI MASAHIRO , KOBAYASHI EIJI , ONOZUKA AKIHIRO , SHIMIZU TOSHIKI
IPC分类号： H04L29/14 , G01R31/02 , G05B23/02 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To detect an incorrect connection of a cable between devices easily and accurately in a system having duplicated communication paths.SOLUTION: A device (arithmetic unit 100) of diagnosis source transmits a test frame destined for each device (input/output unit 103) of communication destination through each one of duplicated communication paths 105a, 106a. Next, on detecting no reception of an identical test frame from any duplicated communication paths, each device (input/output unit 103) of communication destination returns a response frame notifying an abnormality of the communication paths to the device (arithmetic unit 100) of diagnosis source, through both the duplicated communication paths 105b, 106b. Finally, when the device (arithmetic unit 100) of diagnosis source receives the identical response frame from both the duplicated communication paths in response to the test frame transmitted to both the communication paths, and if a predetermined abnormality is notified in the response frame, the device (arithmetic unit 100) of diagnosis source determines that cable connection between the devices configuring the communication paths to the device (input/output unit 103) of communication destination is normal.
摘要翻译：要解决的问题：在具有重复通信路径的系统中，容易且准确地检测设备之间的电缆的不正确连接。解决方案：诊断源的装置（运算单元100）通过复制通信路径105a，106a中的每一个发送目的地是通信目的地的每个设备（输入/输出单元103）的测试帧。接下来，通信目的地的各设备（输入/输出单元103）在从任何复制的通信路径检测到没有接收到相同的测试帧的情况下，返回响应帧，其通知诊断的设备（运算单元100）的通信路径的异常源，通过复制的通信路径105b，106b。最后，当诊断源的设备（运算单元100）响应于发送到两个通信路径的测试帧，从复制的通信路径接收到相同的响应帧时，如果在响应帧中通知了预定的异常，则诊断源的设备（运算单元100）确定构成通信目的地的设备（输入/输出单元103）的通信路径的设备之间的电缆连接正常。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2011150590A Solid state drive device and reconfiguration method of mirror configuration 有权
标题翻译：固态驱动器件和镜像配置的重新配置方法
公开(公告)号：JP2011150590A
公开(公告)日：2011-08-04
申请号：JP2010012203
申请日：2010-01-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NISHIMURA TAKAMASA , SHIRAISHI MASAHIRO , MATSUDA KOJI
IPC分类号： G06F12/16 , G06F3/06 , G06F3/08
CPC分类号： G06F3/065 , G06F3/0617 , G06F3/0688 , G06F11/108 , G06F11/2079 , G06F11/2084 , G06F11/2087
摘要： PROBLEM TO BE SOLVED: To provide an SSD device having a mirror configuration, which can improve availability and suppress cost. SOLUTION: An SSD device 1 includes: a nonvolatile data storage part 20 having the mirror configuration composed of an (A) system and a (B) system; and a nonvolatile data storage control part 10. The nonvolatile data storage control part 10 includes: a page read/write control part 11; an address conversion processing part 13; a physical address selection processing part 14; and an address conversion table 15. On detection of a fault in an NVM chip 21, the page read/write control part 11 reads a page data from the NVM chip 21 having mirror relationship with the fault NVM chip 21, and copies the readout page data to NVM chips 21, which respectively belong to the (A) system and the (B) system in the nonvolatile data storage part 20 and mutually have mirror relationship, other than the fault NVM chip 21 and the NVM chip 21 having mirror relationship with the fault NVM chip 21. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有镜像配置的SSD设备，其可以提高可用性并抑制成本。解决方案：SSD设备1包括：具有由（A）系统和（B）系统组成的镜像配置的非易失性数据存储部分20; 和非易失性数据存储控制部分10.非易失性数据存储控制部分10包括：页面读/写控制部分11; 地址转换处理部13; 物理地址选择处理部分14; 和地址转换表15.在检测到NVM芯片21中的故障时，页面读/写控制部分11从与故障NVM芯片21具有镜像关系的NVM芯片21读取页数据，并将读出页复制数据分别属于非易失性数据存储部20中的（A）系统和（B）系统的NVM芯片21，并且与具有镜像关系的故障NVM芯片21和NVM芯片21之间的相互具有镜像关系故障NVM芯片21.版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2009005412A Control device, control method, and control program 审中-公开
标题翻译：控制装置，控制方法和控制程序
公开(公告)号：JP2009005412A
公开(公告)日：2009-01-08
申请号：JP2008247058
申请日：2008-09-26
申请人： Hitachi Information & Control Solutions Ltd , Hitachi Ltd , 株式会社日立情報制御ソリューションズ , 株式会社日立製作所
发明人： ONOZUKA AKIHIRO , BANDO AKIRA , KOBAYASHI MASAMITSU , SHIRAISHI MASAHIRO , OGURA MAKOTO , UMEHARA TAKASHI , KOBAYASHI EIJI , FUNAKI SATORU , ISHIKAWA MASAKAZU , FURUTA YASUYUKI , NAKANO AKIHIRO , MASUKO NAOYA , OZAWA SHOICHI , KASAHARA TAKENORI , SEKI YUSUKE , OTANI TATSUYUKI , IWASAKI YU
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a communication control device whose transfer performance is not reduced, even when transfer via a line is made, without adding a counter to a plurality of input modules, in a process control system.
SOLUTION: A time counter is provided in a destination communication control device. Furthermore, an input buffer for temporarily storing input data and a time buffer that temporarily stores the time counted value of the time counter are provided in the destination communication control devices. These buffers are simultaneously allowed to update data. The destination communication control device has a means for transmitting a single time value and a plurality of input values. A source communication control device has a means for expanding a single time value into a plurality of input values.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种不降低传送性能的通信控制装置，即使在通过线路传输的情况下，也不在多个输入模块中添加计数器，在过程控制系统中。解决方案：在目的地通信控制设备中提供时间计数器。此外，在目的地通信控制装置中设置用于临时存储输入数据的输入缓冲器和临时存储时间计数器的时间计数值的时间缓冲器。同时允许这些缓冲区更新数据。目的地通信控制装置具有用于发送单个时间值和多个输入值的装置。源通信控制装置具有用于将单个时间值扩展成多个输入值的装置。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008299767A Diagnostic device and diagnostic method 有权
标题翻译：诊断装置及诊断方法
公开(公告)号：JP2008299767A
公开(公告)日：2008-12-11
申请号：JP2007147692
申请日：2007-06-04
申请人： Hitachi Information & Control Solutions Ltd , Hitachi Ltd , 株式会社日立情報制御ソリューションズ , 株式会社日立製作所
发明人： OTANI TATSUYUKI , BANDO AKIRA , OGURA MAKOTO , SAKATA TERUAKI , KOBAYASHI EIJI , ONOZUKA AKIHIRO , KOBAYASHI MASAMITSU , FUNAKI SATORU , FURUTA YASUYUKI , ISHIKAWA MASAKAZU , SHIRAISHI MASAHIRO
IPC分类号： G06F11/22 , G06F11/18
摘要： PROBLEM TO BE SOLVED: To improve the entire failure detection rate by performing failure detection without depending on an output of a processing part and performing failure detection of a comparing part for performing the failure detection without limiting execution timing. SOLUTION: This diagnostic device is provided with the comparing part for detecting a failure of processing parts by comparing two pieces of output information output from duplicated two processing parts, a failure information injecting part for injecting pseudo failure information so that the comparing part may detect the processing parts have a failure into the comparing part, and a failure determination part for performing failure determination of the comparing part by using a detection result of the comparing part to which the pseudo failure information is injected. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过执行故障检测来提高整个故障检测率，而不依赖于处理部分的输出，并且在不限制执行定时的情况下执行用于执行故障检测的比较部分的故障检测。解决方案：通过比较从复制的两个处理部分输出的两条输出信息，用于注入伪故障信息的故障信息注入部分，使得该诊断装置具有用于检测处理部分的故障的比较部分，使得比较部分可以将处理部分检测到失败到比较部分，以及故障确定部分，用于通过使用注射了伪故障信息的比较部分的检测结果来执行比较部分的故障确定。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2008059448A Bus system and bus system control method 审中-公开
标题翻译：总线系统和总线系统控制方法
公开(公告)号：JP2008059448A
公开(公告)日：2008-03-13
申请号：JP2006237710
申请日：2006-09-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKATA TERUAKI , SHIMAMURA KOTARO , BANDO AKIRA , KOBAYASHI MASAMITSU , SHIRAISHI MASAHIRO , OGURA MAKOTO , KOBAYASHI EIJI , SEKI YUSUKE
IPC分类号： G06F13/36
CPC分类号： G06F11/364
摘要： PROBLEM TO BE SOLVED: To provide a bus system capable of guaranteeing the reliability of transfer data even though abnormality occurs in a master or a slave uninvolved in transfer during transferring data whose reliability should be guaranteed in the bus system in which a plurality of masters 1 and 2 and slaves 3 and 4 are connected to a bus 5.
SOLUTION: The bus system is provided with bus switches 31 to 34 and a switch control part 11. During priority (security) data transfer, a priority (security) data signal 71 is defined as "1", and bus switches 32 and 34 of the master 2 and the slave 4 uninvolved in the transfer are turned off, and while during normal data transfer, the priority (security) data signal 71 is defined as "0", and all of the bus switches 31 to 34 are turned on.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种能够保证传送数据的可靠性的总线系统，即使在传输中的主机或从机中的异常发生，在传输数据时，其可靠性应当在总线系统中保证，其中多个主机1和2以及从机3和4连接到总线5.解决方案：总线系统设置有总线开关31至34和开关控制部分11.在优先级（安全性）数据传输期间，优先级（安全性）数据信号71被定义为“1”，并且主机2的总线开关32和34以及从动装置4中不涉及传送的总线开关32和34被关断，而在正常的数据传输期间，优先级（安全性）数据信号71 被定义为“0”，并且所有总线开关31至34都被接通。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007067761A Communication control method, communication control apparatus, and communication control system 审中-公开
标题翻译：通信控制方法，通信控制装置和通信控制系统
公开(公告)号：JP2007067761A
公开(公告)日：2007-03-15
申请号：JP2005250495
申请日：2005-08-31
申请人： Hitachi Information & Control Solutions Ltd , Hitachi Ltd , 株式会社日立情報制御ソリューションズ , 株式会社日立製作所
发明人： ONOZUKA AKIHIRO , SHIRAISHI MASAHIRO , KOBAYASHI MASAMITSU , OGURA MAKOTO , UMEHARA TAKASHI , ISHIKAWA MASAKAZU , KOBAYASHI EIJI , FURUTA YASUYUKI , ENDO HIROMICHI , FUNAKI SATORU , BANDO AKIRA
IPC分类号： H04L1/14 , H04L12/707 , H04L12/813 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To provide a communication control apparatus capable of reducing an oversight error rate and carrying out masquerade detection over security functions in a process control system. SOLUTION: A data receiver side applies echo-back transmission to data, a data transmission source collates the data and informs a result of the collation of the data receiver side. The communication control apparatus comprises: a master communication control apparatus; and a slave communication control apparatus connected to an output circuit, the master communication control apparatus transmits output data, the slave communication control apparatus transmits echo-back of the output data, and the master communication control apparatus collates the output data with the echo-back and permits an output to the slave communication control apparatus when they are coincident. The communication control apparatus comprises the master communication control apparatus and the slave communication control apparatus connected to an input circuit, the slave communication control apparatus transmits input data, the master communication control apparatus transmits echo-back of the input data, and the slave communication control apparatus collates the input data and the echo-back and permits an input to the master communication control apparatus when they are coincident. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够降低监视错误率并且在过程控制系统中对安全功能执行伪装检测的通信控制装置。解决方案：数据接收机侧对数据应用回波传输，数据传输源对数据进行比较并通知数据接收机侧的核对结果。通信控制装置包括：主通信控制装置; 以及连接到输出电路的从属通信控制装置，主通信控制装置发送输出数据，从属通信控制装置发送输出数据的回波，主通信控制装置将输出数据与回波并且当从属通信控制装置重合时允许输出到从通信控制装置。通信控制装置包括连接到输入电路的主通信控制装置和从通信控制装置，从通信控制装置发送输入数据，主通信控制装置发送输入数据的回波和从通信控制装置对输入数据和回波进行整理，并且当它们重合时允许对主通信控制装置的输入。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2011149855A Electronic circuit device and method for supporting operation verification thereof 有权
标题翻译：电子电路装置及其操作验证方法
公开(公告)号：JP2011149855A
公开(公告)日：2011-08-04
申请号：JP2010011934
申请日：2010-01-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YOSHINAGA TAKASHI , SHIRAISHI MASAHIRO , NISHIMURA TAKAMASA , MATSUDA KOJI
IPC分类号： G01R31/28 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To allow a designer to readily conduct operation verification on a device. SOLUTION: A verification support processing circuit 22 of an electronic circuit device 100 generates verification control information for controlling verification of a functional block circuit 1, based on verification indication information to be transmitted from an electronic circuit verification device 200, and transmits the verification control information to the functional block circuit 1. The functional block circuit 1, upon receiving the verification control information, injects an optional status code and an error status to be specified by the verification control information to a status code register, and an error status register of the functional block circuit 1, via a transition stop control circuit 40; and a status code injection circuit 50 and an error status injection circuit 80 and starts or stops operations of the functional block circuit 1. A status history storage circuit 60 stores the history of the status code of that time and of the state code of the latest number of predetermined operation cycles in the past. The verification support processing circuit 22 acquires and transmits the status code history to the electronic circuit verification device 200. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：允许设计者容易地在设备上进行操作验证。解决方案：电子电路装置100的验证支持处理电路22基于要从电子电路验证装置200发送的验证指示信息，生成用于控制功能块电路1的验证的验证控制信息，并发送验证控制信息发送到功能块电路1.功能块电路1在接收到验证控制信息时，将由验证控制信息指定的可选状态代码和错误状态注入到状态代码寄存器和错误状态功能块电路1的寄存器，经由过渡停止控制电路40; 状态码注入电路50和错误状态注入电路80，并且启动或停止功能块电路1的操作。状态历史存储电路60存储该时间的状态码和最新的状态码的历史过去的预定操作周期数。验证支持处理电路22获取并发送状态码历史给电子电路验证装置200.版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2011138243A Storage device and method for controlling storage device 有权
标题翻译：存储装置和用于控制存储装置的方法
公开(公告)号：JP2011138243A
公开(公告)日：2011-07-14
申请号：JP2009296667
申请日：2009-12-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NISHIMURA TAKAMASA , SHIRAISHI MASAHIRO , MATSUDA KOJI
IPC分类号： G06F12/16
CPC分类号： G06F11/1666 , G06F11/20
摘要： PROBLEM TO BE SOLVED: To provide a redundant storage device that maintains reliability while improving a data transfer speed and the limited number of rewrites.
SOLUTION: The storage device includes systems A and B each configured of a plurality of non-volatile semiconductor elements (NAND-Flash 7) connected to a plurality of buses (buses 0 to 3). The non-volatile semiconductor elements are associated with each other such that when the buses (buses 0 to 3) in the system A connected to the non-volatile semiconductor elements (NAND-Flash 7) are changed, the buses (buses 4 to 7) in the system B connected to the non-volatile semiconductor elements are changed, accordingly. In response to a write request or a read request, the non-volatile semiconductor element (NAND-Flash 7) in one of the systems A and B is selected such that the non-volatile semiconductor element (NAND-Flash 7) connected to the same bus is not repeatedly selected. The non-volatile semiconductor element (NAND-Flash 7) in the other system is selected based on its association with the selected non-volatile semiconductor element (NAND-Flash 7).
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种在提高数据传输速度和有限数量的重写的同时保持可靠性的冗余存储设备。解决方案：存储设备包括系统A和B，系统A和B各自由连接到多个总线（总线0至3）的多个非易失性半导体元件（NAND闪存7）构成。非易失性半导体元件彼此相关联，使得当连接到非易失性半导体元件（NAND闪存7）的系统A中的总线（总线0至3）改变时，总线（总线4至7 ）相应地改变连接到非易失性半导体元件的系统B中。响应于写入请求或读取请求，选择系统A和B之一中的非易失性半导体元件（NAND闪存7），使得连接到所述非易失性半导体元件相同的总线不被重复选择。基于与所选择的非易失性半导体元件（NAND-Flash 7）的关联来选择另一系统中的非易失性半导体元件（NAND闪存7）。版权所有（C）2011，JPO＆INPIT

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