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1. 发明专利

JPS5967653A Multilayer wiring and manufacture thereof 失效
标题翻译：多层接线及其制造
公开(公告)号：JPS5967653A
公开(公告)日：1984-04-17
申请号：JP17768682
申请日：1982-10-12
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： OOWADA NOBUO , NAKADA KENSUKE , SASABE SHIYUNJI , MORI TAKAAKI , ANZAI AKIO , HATSUTA YASUSHI , HOSOE HIDEYUKI , NISHINA TATSUFUMI
IPC分类号： H01L21/3205 , H01L21/28
摘要： PURPOSE:To connect both a first wiring layer and a second wiring layer mutually and excellently by forming the shape of a through-hole to a shape in which an arcuate indentation and a columnar hole are combined when the through-hole is formed to an interposing insulating layer and both wiring layers are connected. CONSTITUTION:A first layer 3 is formed on a substrate 1, to which a diffusion layer is formed, through an insulating film 2. A insulating film 4 is formed on the wiring layer 3, and the arcuate indentation 7 is formed to the insulating film 4 by using a resist 5. The columnar hole 8 is formed to the indentation 7 through anisotropic etching. The resist 5 is removed, and a second electrode layer 9 is formed on the insulating film 4 and the hole 8. According to such constitution, the first wiring layer 3 can be coated excellently with the second wiring layer 9.
摘要翻译：目的：通过将通孔的形状形成为通孔形成为插入状态的弓形凹部和柱状孔组合的形状，将第一布线层和第二布线层相互良好地连接绝缘层和两个布线层连接。构成：第一层3通过绝缘膜2形成在其上形成有扩散层的基板1上。在布线层3上形成绝缘膜4，并且在绝缘膜上形成弓形凹部7 通过使用抗蚀剂5，通过各向异性蚀刻将柱状孔8形成在凹部7上。除去抗蚀剂5，在绝缘膜4和孔8上形成第二电极层9.根据这样的结构，能够与第二布线层9一体地涂布第一布线层3。

2. 发明专利

JPS60245252A MULTILAYER INTERCONNECTION MEMBER 失效
公开(公告)号：JPS60245252A
公开(公告)日：1985-12-05
申请号：JP10045984
申请日：1984-05-21
申请人： HITACHI LTD
发明人： KASAHARA OSAMU , SASABE SHIYUNJI
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To improve the reliability of the titled member by a method wherein the second conductive layer serving as an etching stopper is provided on the first conductive layer, and the insulation between the second layer wiring and the third layer wiring is improved by homogenizing the insulation film covering the second layer wiring. CONSTITUTION:A field insulation layer 2 and an insulation layer 3 are formed in the main surface part of a required region of a substrate 1. The first layer wiring 4 is formed in a required region of the upper surface part of the insulation layer 3; thereafter, an insulation layer 5 is formed. Conductive layers 7, 7A are formed to fill a connection hole 6, and conductive layers 8, 8A made of Cu or Cu alloy are formed on the conductive layers 7, 7A to form an etching inhibition member 8. After the photo resist layer 13 on this member 8 is removed, the second layer wiring 9 is formed. Thereafter, the second layer wiring 10 and the third layer wiring 11 are formed. Since an eye open 9A does not allow the formation of crevasses in the second layer wiring 9 and the third layer wiring 11, the film quality of the second insulation layer 10 is made uniform, and the electric insulation of those layers can be improved.

3. 发明专利

JPS59192904A Device for measuring film thickness 失效
标题翻译：用于测量薄膜厚度的装置
公开(公告)号：JPS59192904A
公开(公告)日：1984-11-01
申请号：JP6544683
申请日：1983-04-15
申请人： Hitachi Ltd
发明人： SASABE SHIYUNJI , TANABE YOSHIKAZU
IPC分类号： G01B11/06 , H01L21/205 , H01L21/66
CPC分类号： G01B11/0616
摘要： PURPOSE:To improve an SN ratio and the measurement precision of film thickness by projecting light from a polarized laser light source upon a film to be measured through a beam splitter and an lambda/4 plate, and detecting interference reflected light by a sensor through a linear polarizing plate. CONSTITUTION:P Polarized light projected by the polarized laser oscillator 14 illuminates an SiO2 film 8 on the surface of a semiconductor wafer 5 through the polarized beam splitter (PBS)15, reflecting mirror 13, view spot glass 12, and lambda/4 plate 11. The interference reflected light travels backward and is reflected by the PBS15 and then detected by the photosensor 18 through the linear polarizing plate 16 and an interference filter 17. Its detection output is processed by a microcomputer 21 through an amplifier 19 and an AD converter 20 to calculate the film thickness. Noise light reflected by the PBS15 and view spot glass 12 is cut off by the linear polarizing plate 16 and the spectrum width is restricted by the interference filter 17, so the SN ratio is improved and the measurement precision of the film thickness is also improved.
摘要翻译：目的：通过将来自偏振激光光源的光投射到通过分束器和λ/ 4板测量的膜上，通过传感器检测干涉反射光，来提高SN比和测量精度线偏振片。构成：P由偏振激光振荡器14投影的偏振光通过偏振分束器（PBS）15，反射镜13，视点玻璃12和λ/ 4板11照射半导体晶片5的表面上的SiO 2膜8 干涉反射光向后行进并被PBS15反射，然后由光电传感器18通过线性偏振板16和干涉滤光器17检测。其检测输出由微型计算机21通过放大器19和AD转换器20 以计算膜厚度。由PBS15和观察点玻璃12反射的噪声光被线偏振片16切断，光谱宽度受到干涉滤光器17的限制，因此提高了SN比，并提高了膜厚的测量精度。

4. 发明专利

JPS59161048A Manufacture of multilayer interconnection member 失效
标题翻译：多层互连会员的制造
公开(公告)号：JPS59161048A
公开(公告)日：1984-09-11
申请号：JP3454783
申请日：1983-03-04
申请人： Hitachi Ltd
发明人： HOSOE HIDEYUKI , TAKAHASHI TAKAHIKO , SASABE SHIYUNJI
IPC分类号： H01L23/522 , H01L21/31 , H01L21/314 , H01L21/768
摘要： PURPOSE:To prevent the generation of a crevasse section, and to improve the reliability of connection between wirings by making the etching rate of an upper insulating film faster than the upper surface section of a first wiring and using a lower insulating film as a stopper on etching for a through-hole. CONSTITUTION:An insulating film 2, a first wiring 3 and an insulating film 4 are formed to a semiconductor substrate 1, impurity ions, such as B ions, P ions, etc. are implanted to change the insulating film 4 formed to a section upper than the upper surface section of the first wiring 3 into an insulating film 4A, an etching rate thereof is faster, and a through-hole 5 is formed through etching. A second wiring 6 is shaped through the through-hole 5. The coatability of the second wiring 6 is improved because a crevasse section is hardly generated, and a connection with the first wiring 3 is enhanced extremely.
摘要翻译：目的：为了防止裂缝部分的产生，并且通过使上绝缘膜的蚀刻速度比第一布线的上表面部分的蚀刻速度快并且使用下绝缘膜作为塞子来提高布线之间的连接的可靠性蚀刻通孔。构成：在半导体衬底1上形成绝缘膜2，第一布线3和绝缘膜4，注入诸如B离子，P离子等的杂质离子，以将形成在上部的绝缘膜4 比第一配线3的上表面部分变成绝缘膜4A，其蚀刻速度更快，并且通过蚀刻形成通孔5。第二布线6通过通孔5成形。由于几乎不产生裂缝部分，因此第二布线6的涂布性得到改善，并且与第一布线3的连接极大地增强。

5. 发明专利

JPS59107539A Manufacture of multilayer wiring 失效
标题翻译：多层布线的制造
公开(公告)号：JPS59107539A
公开(公告)日：1984-06-21
申请号：JP21692382
申请日：1982-12-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HOSOE HIDEYUKI , OOWADA NOBUO , SASABE SHIYUNJI , YAMASHITA MICHIO
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768
摘要： PURPOSE:To obtain the multilayer wiring which is securely connected by a method wherein the first wiring with a protruded part is formed on a substrate, an insulating film is superposed thereon, and the second wiring is superposed on the above by connecting it to the exposed protruded part. CONSTITUTION:An Al wiring layer 3 is selectively formed on the SiO2 film 2 located on an Si substrate 1, an Al layer 4 of the same thickness as above is superposed, and an underlying wiring is formed. Then, after an SiO2 film 5 has been coated on the above by performing a planar type bias sputtering and a flow discharge in Ar, an HF type dry etching process is conducted on the whole surface, and the upper surface of the wiring 4 is exposed. Subsequently, an upper wiring 6 of Al is provided perpendicular to the surface of paper, an SiO2 film 7 is formed again using a planar type bias-sputtering technique, and the multilayer wiring is completed. According to this constitution, an etching can be controlled easily in a highly accurate manner, because an interlayer insulating film is flatly formed, an interlayer connection part in the measurements same as the underlying wiring, and the allowable measurements of mask displacement can be unnecessitated, thereby enabling to improve the degree of integration of the multilayer wiring.
摘要翻译：目的：为了获得通过其中在基板上形成具有突出部分的第一布线的方法可靠地连接的多层布线，绝缘膜叠加在其上，并且第二布线通过将其连接到暴露的突出部分。构成：在位于Si衬底1上的SiO 2膜2上选择性地形成Al布线层3，将与上述厚度相同的Al层4重叠，形成底层布线。然后，在通过进行平面型偏压溅射和Ar中的流量放电之后涂覆了SiO 2膜5之后，在整个表面上进行HF型干蚀刻工艺，并且布线4的上表面暴露。随后，垂直于纸表面设置Al的上布线6，利用平面型偏压溅射技术再次形成SiO 2膜7，并完成多层布线。根据该构造，由于层间绝缘膜平坦地形成，与下层布线相同的测量结果中的层间连接部分，并且可能不需要掩模位移的允许测量，因此可以以高精度的方式容易地控制蚀刻，从而能够提高多层配线的集成度。

6. 发明专利

JPS5571089A METHOD OF CLEANING THROUGH HOLE PORTION 失效
公开(公告)号：JPS5571089A
公开(公告)日：1980-05-28
申请号：JP14418178
申请日：1978-11-24
申请人： HITACHI LTD
发明人： SATOU MASAYUKI , SASABE SHIYUNJI
IPC分类号： H05K3/46 , H01L21/3213 , H05K3/40

7. 发明专利

JPS60136335A MULTILAYER INTERCONNECTION STRUCTURE 失效
公开(公告)号：JPS60136335A
公开(公告)日：1985-07-19
申请号：JP24382183
申请日：1983-12-26
申请人： HITACHI LTD
发明人： KURODA SHIGEO , TAKAHASHI TAKAHIKO , OOWADA NOBUO , SASABE SHIYUNJI
IPC分类号： H01L23/522 , H01L21/768 , H01L21/88
摘要： PURPOSE:To prevent a faulty short-circuit generating from the coexistence of unnecessary foreign substance as well as to improve the electrical reliability of the titled device by a method wherein an interlayer insulating layer is composed of a silicon nitride layer formed by performing a plasma CVD method and a silicon oxide layer formed by performing a bias sputtering technique. CONSTITUTION:The first layer of wirings 3A, 3B and 3C are formed. Then, when a silicon nitride layer which is formed by performing a plasma CVD technique is used for the first insulating layer 4 which is covered on the wiring 3, a foreign substance 4A is coexisted in the process wherein the first insulating layer 4 is formed. When silicon oxide layer is used for the second insulating layer 5 using a bias sputtering technique, the upper surface part of the layer 5 is flattened, and a foreign substance 5A is coexisted in the process of formation of the second insulating layer 5. After the above-mentioned process has been finished, the insulating layers 4 and 5 located on the upper part of the first layer wiring 3A are selectively removed, and a connecting hole 6 is formed.

8. 发明专利

JPS6057941A SPUTTERING DEVICE 失效
公开(公告)号：JPS6057941A
公开(公告)日：1985-04-03
申请号：JP16498683
申请日：1983-09-09
申请人： HITACHI LTD
发明人： OZAKI MAMORU , SASABE SHIYUNJI
IPC分类号： C23C14/34 , H01L21/31
摘要： PURPOSE:To prevent the generation of cracks in a quartz target, to lengthen life and to form a thin-film having excellent quality by forming a metallic layer integrally shaped to the back of the target by a material, wetting properties thereof with a fixing material are excellent and alloying porperties thereof at the high melting point are low. CONSTITUTION:A Cr layer 17 is integrally formed previously to the back of a quartz board 14, nd the quartz board 14 is fixed to a packing plate 15 by wetting properties between the Cr layer 17 and a fixing material 16 (an alloy layer of In/Sn). Consequently, thermal stress is not concentrated because heat generated by a collision and a reaction with the quartz board 14 of Ar ions is dissipated rapidly to the packing plate 15 through the Cr layer 17 and the In/Sn alloy layer 16 and there is no air gap at that time. Accordingly, the generation of cracks in the quartz board 14 can be prevented, and the generation of foreign matters and a contamination to a formed film can be obviated.

9. 发明专利

JPS59182541A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59182541A
公开(公告)日：1984-10-17
申请号：JP5509083
申请日：1983-04-01
申请人： Hitachi Ltd
发明人： SASABE SHIYUNJI
IPC分类号： H01L21/3213 , H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3065
摘要： PURPOSE:To enable to perform monitoring, and to perform etching correctly when an interlayer film formed between underside layers and topside layers are to be etched by a method wherein dummy underside layers are formed by the same condition at the sites not necessitating the underside layers, and the film on the dummy underside layers is etched at the same time when the interlayer film is etched. CONSTITUTION:A semiconductor substrate 10 is divided into respective chip regions 11 and a scribe line region 12, circuit elements of various kinds are provided in the regions 11, and the surface of the insulating layer is left to be exposed. Then first Al layers 13 of underside layers are adhered on the regions 11 to form the prescribed circuit patterns, while at the same time, first Al layers 13a of dummy underside layers are formed also on the region 12. After then, the whole surface is covered with an SiO2 interlayer insulating film 15, and etching is performed to remove the film 15 on the layer 13, 13a using a resist mask 16 having the prescribed shape. Accordingly, the layers 13a are exposed when through holes 17 are dug on the layers 13, monitoring is performed accurately when the holes 17 are formed, and second Al layers 18 are adhered thereto.
摘要翻译：目的：为了在通过下述方法蚀刻形成下层和顶层之间的层间膜时，能够进行监控，并进行正确的蚀刻，其中在不需要下层的位置处，通过相同的条件形成虚设的下侧层，并且在蚀刻层间膜的同时，在虚拟下侧层上的膜被蚀刻。构成：将半导体基板10分割成各个芯片区域11和划线区域12，在区域11中设置各种电路元件，并且使绝缘层的表面露出。然后，第一层的下层13的Al层13粘附在区域11上以形成规定的电路图案，同时在区域12上也形成虚拟下侧层的第一Al层13a。之后，整个表面是覆盖有SiO 2层间绝缘膜15，并且使用具有规定形状的抗蚀剂掩模16进行蚀刻以去除层13,13a上的膜15。因此，当在层13上挖出通孔17时，暴露层13a，当形成孔17时准确地进行监测，并且将第二Al层18粘附到其上。

10. 发明专利

JPS5984549A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5984549A
公开(公告)日：1984-05-16
申请号：JP19470782
申请日：1982-11-08
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： HIRANO NOBUAKI , SASABE SHIYUNJI
IPC分类号： H01L23/522 , H01L21/306 , H01L21/768
摘要： PURPOSE:To inhibit the depth of a through-hole to some extent, and to execute the inter-layer connection of a multilayer wiring positively by forming a notch section to a lower layer wiring section constituting the mutilayer wiring and thinning the thickness of the inter-layer insulating film of a through-hole section. CONSTITUTION:The notch sections in which there exists no wiring layer, grooves 6, are formed to the pad section 2 of a flat lower layer wiring layer of a large area. Consequently, since the width (width among the grooves 6 and the periphery of the pad) of the wiring layer of the pad section is thin, silicon oxide on thin sections does not thicken even when the pad section is coated with silicon oxide. As a result, when the through-holes 4 are formed to the thin sections, the quantity of etching can be reduced, and the depth of the through-holes can be inhibited to some extent. Accordingly, the generation of a breaking at a step of the wiring 5 or the situation in which the wiring 5 is narrowly connected by a thin-film can be prevented, and wiring layers are connected to each other positively.

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