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1. 发明授权

US4721984A VOLTAGE REGULATOR DIODE 失效
标题翻译：电压调节器二极管
公开(公告)号：US4721984A
公开(公告)日：1988-01-26
申请号：US66484684
申请日：1984-10-25
申请人： HITACHI LTD
发明人： TOITA HIROTOSHI , HIDAKA TOSHIYUKI , SAKAMOTO HISASHI
IPC分类号： H01L29/866 , H01L29/36 , H01L29/861 , H01L29/90
CPC分类号： H01L29/36 , H01L29/861

2. 发明专利

CA1206819A RESIN-MOLDED SEMICONDUCTOR DEVICE AND A PROCESS FOR MANUFACTURING THE SAME 未知
公开(公告)号：CA1206819A
公开(公告)日：1986-07-02
申请号：CA443800
申请日：1983-12-20
申请人： HITACHI LTD
发明人： HIDAKA TOSHIYUKI , SAKAMOTO HISASHI , FUKUHARA TOSHIAKI , FUJIEDA SADAO , MISAWA YUTAKA
IPC分类号： C08G59/00 , C08G59/20 , H01L21/56 , H01L23/29 , H01L23/31 , H01L23/30
摘要： : The invention provides a process for manufacturing a semiconductor device and the semiconductor device so produced. In particular, the process permits a semiconductor pellet to be sealed in an epoxy resin in a manner that does not require the use of a mold. The epoxy resin is dropped onto the pellet as the pellet is turned. The epoxy resin its then heated at 160-180.degree.C for 2 to 10 minutes as the pellet is turned, so that the surface portions of the epoxy resin are hardened. The resin is then heated at 160-200.degree.C for 3 to 24 hours while the pellet is kept stationary in order to complete the hardening of the resin. The avoidance of the use of a mold means that a very satisfactory device can be mass produced quickly and efficiently.

3. 发明专利

DE2329475A1 未知
公开(公告)号：DE2329475A1
公开(公告)日：1974-01-10
申请号：DE2329475
申请日：1973-06-08
申请人： HITACHI LTD
发明人： NAKASHIMA YOICHI , SAKAMOTO HISASHI , ISHIZUKA TAKESHI , SUZUKI KENSUKE
IPC分类号： H02M7/10 , H01L21/56 , H01L25/11 , H01L1/16
摘要： A combined semiconductor device composed of a plurality of semiconductor elements each molded with an insulating material such that the semiconductor element with lead wires is coated with the insulating material down to an appropriate position of each lead wire so that the remaining part of each lead wire is exposed for connection with other circuit elements, the molded semiconductor elements being connected with each other in a bridged manner with interspaces therebetween by means of an insulating material the same as or similar to the molding material.

4. 发明专利

DE2323896A1 未知
公开(公告)号：DE2323896A1
公开(公告)日：1973-12-13
申请号：DE2323896
申请日：1973-05-11
申请人： HITACHI LTD
发明人： SAKAMOTO HISASHI , SASAKI TAKESHI , MIKAMI SATOSHI , NAKASHIMA YOICHI
IPC分类号： C03C14/00 , H01B3/08 , H01L23/04 , H01L23/29 , H01L23/31 , H01L25/07 , H01L1/02
摘要： A glass mold semiconductor device comprising a semiconductor pellet, a couple of electrodes disposed on both sides of the semiconductor pellet and a glass layer for covering the semiconductor pellet and at least part of the two of electrodes.

5. 发明专利

DE3377438D1 RESIN-MOLDED SEMICONDUCTOR DEVICES AND A PROCESS FOR MANUFACTURING THE SAME 未知
公开(公告)号：DE3377438D1
公开(公告)日：1988-08-25
申请号：DE3377438
申请日：1983-12-20
申请人： HITACHI LTD
发明人： HIDAKA TOSHIYUKI , SAKAMOTO HISASHI , FUKUHARA TOSHIAKI , FUJIEDA SADAO , MISAWA YUTAKA
IPC分类号： C08G59/00 , C08G59/20 , H01L21/56 , H01L23/29 , H01L23/31 , H01L23/30
摘要： The invention relates to resin-molded axial lead-type semiconductor devices comprising a sub-assembly consisting of a semiconductor pellet (1) brazed between a pair of axial leads (5). The sub-assembly is sealed in an epoxy resin, which is formed by applying an epoxy resin, preferably a one-can-epoxy resin, onto the sub-assembly followed by curing the epoxy resin. Preferably, an epoxy resin having a thixotropic index of 1.0 to 2.5 and a gelation time 0.8 to 3 minutes is used. The invention further relates to a process for manufacturing these semiconductor devices which is characterised by: (A) horizontally holding the sub-assembly and dropping a predetermined amount of an epoxy resin onto the semiconductor pellet while turning the sub-assembly with the axial leads as rotation axis, (B) curing the epoxy resin, preferably by heating at 160 DEG to 180 DEG for a period of 2 to 10 min, while turning the sub-assembly, so that the surface portions of the epoxy resin are cured, and (C) curing the epoxy resin, preferably by heating at 160 DEG to 200 DEG C for a period of 3 to 24 h while maintaining the sub-assembly stationary without turning it, so that the epoxy resin is completely hardened.

6. 发明专利

JPS61231745A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61231745A
公开(公告)日：1986-10-16
申请号：JP7380685
申请日：1985-04-08
申请人： HITACHI LTD
发明人： HARADA EIJI , MATSUZAKI HITOSHI , SAKAMOTO HISASHI
IPC分类号： H01L21/52 , H01L23/482 , H01L23/498 , H01L29/74
摘要： PURPOSE:To reduce the mounting area of a semiconductor device, and moreover to improve heat radiation thereof by a method wherein different electrodes of two kinds are formed on the main surface, and semiconductor chips, etc. divided into the plural number and forming fine strip types are provided to the respective electrodes thereof. CONSTITUTION:The plural number of gate electrodes 1a forming a fine strip type and the plural number of cathode electrodes 1b forming similarly the fine strip type are arranged on the main surface of a silicon chip 2 putting the respective longitudinal directions in the same direction and moreover putting alternately in the direction to meet at right angles with the said direction, and an anode electrode 9 is formed on the whole region of the back. Diffusion layers 4, 5, 6, 8 are formed in the silicon chip 2. Moreover, an insulating plate 51 and outside electrodes 53a, 53b are fitted in order on the main surface of the silicon chip, and the outside electrodes 53a, 53b are connected respectively to metal layers 52a, 52b having comparatively large areas on the main surface of the insulating substrate 51. Because the outside lead-out electrodes are so constructed as to enable to be led out through the substrate for leading out of the electrodes, the device can be constructed from a broad plate type metal, and a semiconductor device having a superior heat radiation effect on the main surface of the silicon chip can be obtained.

7. 发明专利

JPS60214546A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS60214546A
公开(公告)日：1985-10-26
申请号：JP7255084
申请日：1984-04-10
申请人： Hitachi Ltd
发明人： HARADA EIJI , SAKAMOTO HISASHI , MATSUZAKI HITOSHI , SAITOU TAKASHI , HIRAYAMA HIDEO
IPC分类号： H01L23/12 , H01L21/52 , H01L21/58 , H01L23/02 , H01L23/13
CPC分类号： H01L23/13 , H01L2224/37147 , H01L2224/3754 , H01L2224/37599 , H01L2224/40 , H01L2224/40091 , H01L2224/40225 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/00012
摘要： PURPOSE:To contrive to eliminate the generaion of a crack and a deficit in the semiconductor substrate by a method wherein a space is formed on the side of an electrode plate in the inner wall of the aperture of the ring-shaped insulating material and the semiconductor substrate and the insulating material are not brought into contact with each other by the formation of the space. CONSTITUTION:A ring-shaped insulating material 108 has been performed a chambering work on the side of an anode electrode plate 7 in the inner wall of its aperture and a space S1 has been formed there. The space S1 is formed in a dimension (l2) that a semiconductor substrate 1 doesn't come into contact with the insulating material 108 even through the minimum relative deviation (l1) arised due to the following two: the maximum relative deviation (l1) between the semiconductor substrate 1 and the insulating material 108 due to the dimensional torelance of a positioning jig (not shown in the diagram), which is used when the semiconductor substrate 1 is bonded, parts and so forth; and the thickness (t1) of the semiconductor substrate 1. (Provided that, l2>l1 and t2>t1). Accordingly, there is no possibility that the semiconductor substrate 1 and the insulating material 108 come into contact with each other. As a result, as no contact of both generates even during the time when heat is dropping, no crack and deficit generate in the semiconductor substrate 1.
摘要翻译：目的：通过在环状绝缘材料的孔的内壁上的电极板的侧面形成空间的方法和半导体衬底的半导体衬底中，形成半导体衬底的裂纹和缺陷的方法，基板和绝缘材料不会通过形成空间而彼此接触。构成：已经在其孔的内壁中的阳极板7的侧面上进行了环状绝缘材料108的制作，并且在其中形成了空间S1。空间S1形成在半导体衬底1不与绝缘材料108接触的尺寸（12）中，即使由于以下两个原因而导致的最小相对偏差（l1）：最大相对偏差（l1）由于半导体基板1被接合时使用的定位夹具（图中未示出）的尺寸相关性，在半导体基板1和绝缘材料108之间。和半导体衬底1的厚度（t1）（假设l2> l1和t2> t1）。因此，半导体衬底1和绝缘材料108不可能彼此接触。结果，即使在热量下降的时间内两者的接触也不会产生，在半导体衬底1中不产生裂纹和缺陷。

8. 发明专利

JPS6094780A CONSTANT-VOLTAGE DIODE 失效
公开(公告)号：JPS6094780A
公开(公告)日：1985-05-27
申请号：JP20082783
申请日：1983-10-28
申请人： HITACHI LTD
发明人： TOIDA HIROTOSHI , HIDAKA TOSHIYUKI , SAKAMOTO HISASHI
IPC分类号： H01L29/866 , H01L29/36 , H01L29/861 , H01L29/90
摘要： PURPOSE:To eliminate the influence to the constant voltage characteristic even if a semiconductor substrate is damaged or notched by forming the substrate of a constant-voltage diode in a negative bevel structure. CONSTITUTION:An Si substrate 11 has three layers of a p type layer 11a, an n type layer 11b and an n type layer 11c, p type impurity and n type impurity are diffused from the main surface side to the thin n type Si plate to form a p-n-n type layer structure, and the region to which the impurity is not diffused becomes the layer 11b. The area of the main surface of the layer 11a side becomes smaller than that of the main surface of the layer 11b side, and the side periphery of te substrate 11 is inclined to the main surface. A p-n junction J formed of the layers 11a and 11b is parallel to the main surface, the exposed end of the junction J is acute at the layer 11a side in the angle formed with the side periphery, and the layer 11a has higher impurity density than the layer 11b. Accordingly, the Si substrate 11 has negative bevel structure. The portion that damage or notch feasibly occurs during the manufacturing steps of the substrate 11 is the main surface peripheral edge of the layer 11c side, and even if the damage or notch occurs, it is separated from the junction, thereby hardly causing the decrease in the characteristics.

9. 发明专利

JPS5633167A BRAZING METHOD 失效
公开(公告)号：JPS5633167A
公开(公告)日：1981-04-03
申请号：JP10587579
申请日：1979-08-22
申请人： HITACHI LTD
发明人： FUJIEDA SADAO , SAKAMOTO HISASHI
IPC分类号： B23K3/06 , B23K1/00 , B23K35/02 , B23K35/22
摘要： PURPOSE:To reduce the flow of brazing material thereby simplifying the set for brazing material so as to improve the operation efficiency, by preparing powdered brazing material with a binder to form paste, then by painting the paste at the parts to be brazed, and by joining the parts at high temp. CONSTITUTION:Brazing material is pulverized to a powder from several mu to several tens mu in particle size, and is mixed with, and dispersed in, a binder such as ethylcellulose solvent to manufacture ink. The ink is painted simultaneously at many places of connecting part of base material through a screen etc. to a suitable thiciness, then it is dried to remove the solvent thereby setting brazing material. The connecting material is placed in a high temp. reducing gas atmosphere etc. Hereby joining is performed by the bonding force between molecules and atoms due to brazing material packed in a gap of base material and by alloy formation due to mutual diffusion. This method allows to join precision parts of complex structure easily.

10. 发明专利

JPS51140579A METHOD OF PRODUCING THYRISTOR 失效
公开(公告)号：JPS51140579A
公开(公告)日：1976-12-03
申请号：JP6437575
申请日：1975-05-30
申请人： HITACHI LTD
发明人： SAKAMOTO HISASHI , MORIYAMA KOUICHI
IPC分类号： H01L29/74
摘要： PURPOSE:To provide a method of producing thyristor which would allow a use of a thick wafer without spoiling the characteristics of the thyristor.

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