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1. 发明专利

JP2008015901A Access control method for external storage device, and controller, host system or external storage device performing access control method 有权
标题翻译：用于外部存储设备的访问控制方法和控制器，主机系统或执行访问控制方法的外部存储设备
公开(公告)号：JP2008015901A
公开(公告)日：2008-01-24
申请号：JP2006188151
申请日：2006-07-07
申请人： Hitachi Information & Control Solutions Ltd , Hitachi Ltd , 株式会社日立情報制御ソリューションズ , 株式会社日立製作所
发明人： YOSHIDA KATSUMI , NAKANO YOSHIHIRO , FUKUMARU HIROAKI , HIUGA KAZUHIRO , SUZUKI MASAHIRO
IPC分类号： G06F3/06
摘要： PROBLEM TO BE SOLVED: To provide an access control method for a controller, capable of enabling error recovery processing of HDD without changing the time-out time of a conventional host. SOLUTION: In the controller 20 including a processing part for attaining various functions by a control program through respective interface parts for accessing the host 10 and the HDD 30, the processing part reports an error to the host (U323) without giving reset instruction to the HDD (U322) when a normal response including completion of error recovery processing is not received from the HDD within the time-out time in accessing the HDD based on an access request from the host, and accesses (U325) the HDD again after giving the reset instruction to the HDD (U324) based on a repeated access request from the host (U311). The error recovery processing (U330) of the HDD is completed during this period. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在不改变常规主机的超时时间的情况下实现HDD的错误恢复处理的控制器的访问控制方法。解决方案：在包括用于通过控制程序通过用于访问主机10和HDD 30的各个接口部分实现各种功能的处理部分的控制器20中，处理部分向主机（U323）报告错误而不给出复位基于来自主机的访问请求在超时时间内从HDD接收到包括完成错误恢复处理的正常响应的指令（U322），并再次访问（U325）HDD 在基于来自主机（U311）的重复访问请求给予HDD（U324）的复位指令之后。在此期间完成HDD的错误恢复处理（U330）。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008152552A Computer system and failure information management method 审中-公开
标题翻译：计算机系统与故障信息管理方法
公开(公告)号：JP2008152552A
公开(公告)日：2008-07-03
申请号：JP2006340158
申请日：2006-12-18
申请人： Hitachi Information & Control Solutions Ltd , Hitachi Ltd , 株式会社日立情報制御ソリューションズ , 株式会社日立製作所
发明人： KAGAYA SHUNICHI , OSONOI HIDEKI , TAKEWA HIDEHITO , HIUGA KAZUHIRO , YASUNAGA TERUYUKI
IPC分类号： G06F11/20 , G06F11/16 , G06F11/30
摘要： PROBLEM TO BE SOLVED: To avoid the problem that a normally operating computer is restarted by mistake since the physical path of each computer is made duplex configurations, and to manage the failure generation information of a plurality of computers.
SOLUTION: A plurality of computers 100 are provided with a BMC 114 for controlling a communication controller 112, and an SVP 140 is connected through a network to a BMC 114 for monitoring the BMC 114. An RAS-U141 collates failure information transmitted from the plurality of computers 100 from the SVP 140, and manages the failure information while performing processing to the failure information. An operation machine 143 transmits an operation request signal including the switching, stop and restart of the computer corresponding to the failure information to the RAS-U141 on the basis of the processing result of the failure information.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了避免由于每台计算机的物理路径被做成双工配置，并且管理多台计算机的故障生成信息，错误地重启正常操作的计算机的问题。解决方案：多个计算机100设置有用于控制通信控制器112的BMC 114，并且SVP 140通过网络连接到BMC 114以用于监视BMC 114. RAS-U141整理发送的故障信息来自SVP 140的多个计算机100，并且在对故障信息进行处理的同时管理故障信息。操作机143根据故障信息的处理结果向RAS-U141发送包括与故障信息对应的计算机的切换，停止和重新启动的操作请求信号。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2008003731A Information processing system 审中-公开
标题翻译：信息处理系统
公开(公告)号：JP2008003731A
公开(公告)日：2008-01-10
申请号：JP2006170850
申请日：2006-06-21
申请人： Hitachi Information & Control Solutions Ltd , Hitachi Ltd , 株式会社日立情報制御ソリューションズ , 株式会社日立製作所
发明人： KAGAYA SHUNICHI , OSONOI HIDEKI , TAKEWA HIDEHITO , HIUGA KAZUHIRO , YASUNAGA TERUYUKI
IPC分类号： G06F11/16 , H04L12/28 , H04L12/40
摘要： PROBLEM TO BE SOLVED: To restore a faulty LAN controller to a normal state or stop it, while a LAN driver 222 informs an other-system monitoring program 212 of excess interruption when the amount of interruption is a threshold or more of the LAN driver 222 (301), the other-system monitoring program 212 transmits an LAN reset request for restarting the faulty LAN controller 251 to the BMC 114 (303), and the BMC 114 issues a LAN reset to a LAN board 115 (305) when the LAN reset request is transmitted from the other-system monitoring program 212 to the BMC 114.
SOLUTION: When the LAN reset is the threshold or more (307), the LAN driver 222 informs the other-system monitoring program 212 of excess LAN reset, and the other-system monitoring program 212 transmits a LAN reset stop request for stopping the faulty LAN controller 251 to the BMC 114 (308).
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了将有故障的LAN控制器恢复到正常状态或停止，LAN驱动程序222通知其他系统监视程序212超量中断时，当中断量为阈值以上时 LAN驱动器222（301），另一系统监视程序212向BMC 114（303）发送用于重新启动故障LAN控制器251的LAN复位请求，并且BMC 114向LAN板115（305）发出LAN复位，当LAN复位请求从其他系统监视程序212发送到BMC 114时。解决方案：当LAN复位为阈值以上时（307），LAN驱动器222通知另一系统监视程序212 的多余LAN复位，而另一系统监视程序212将用于停止故障的LAN控制器251的LAN复位停止请求发送到BMC 114（308）。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007058708A Multiplex system 有权
标题翻译： MULTIPLEX系统
公开(公告)号：JP2007058708A
公开(公告)日：2007-03-08
申请号：JP2005245319
申请日：2005-08-26
申请人： Hitachi Information & Control Solutions Ltd , Hitachi Ltd , 株式会社日立情報制御ソリューションズ , 株式会社日立製作所
发明人： KAGAYA SHUNICHI , OSONOI HIDEKI , HIUGA KAZUHIRO , TAKEBAYASHI TAKESHI , OSONO NOBUYUKI
IPC分类号： G06F11/20 , G06F11/16 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To inexpensively construct a highly reliable multiplex system in a short period, in which faults can be mutually monitored between computers and quickly restored independently of the loads of a network between the computers, by utilizing general technology such as a general network and general computers.
SOLUTION: In order to mutually monitor between a plurality of computers, two independent routes, i.e. a general LAN1 102 and a general LAN2 103, are used. Network drivers also are separated into two parts corresponding to respective routes 102, 103. Inner buses are separated into a management bus 120 in which a telegram flow rate is fixed and which is used for controlling a CPU and an extension bus 121 in which a telegram flow rate is changed and which is used for communication with the CPU. A driver of a system switching control (LXP) board 116 transmits/receives fault information signals by a poling method without executing interruption processing 118. The system switching control (LXP) board 116 is provided with a CPU restart (reset) function from the other system, a CPU stop function from the other system and a CPU stop function of its own system.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了在短时间内廉价地构建高度可靠的多路复用系统，其中可以在计算机之间相互监测故障并且能够独立于计算机之间的网络的负载快速恢复，通过利用诸如一般网络和一般电脑。解决方案：为了在多个计算机之间相互监视，使用两个独立的路由，即通用LAN1102和通用LAN2103。网络驱动器还被分成对应于相应路线102,103的两个部分。内部总线被分成管理总线120，其中电报流速是固定的，并且用于控制CPU和延长总线121，其中电报流量变化，用于与CPU进行通信。系统切换控制（LXP）板116的驱动器通过极化方式发送/接收故障信息信号而不执行中断处理118.系统切换控制（LXP）板116被提供有来自另一个的CPU重启（复位）功能系统，其他系统的CPU停止功能和自己系统的CPU停止功能。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2000031839A HIGHLY RELIABLE DATA TRANSMITTER AND SYSTEM THEREFOR 失效
公开(公告)号：JP2000031839A
公开(公告)日：2000-01-28
申请号：JP19696798
申请日：1998-07-13
申请人： HITACHI LTD
发明人： OSONOI HIDEKI , ARAOKA MANABU , HIUGA KAZUHIRO
IPC分类号： H04B1/74 , H04B1/04
摘要： PROBLEM TO BE SOLVED: To prevent data from being erroneously transmitted even when power is inputted by providing a data transmission inhibit circuit which allows data to be transmitted until an power output is stabilized and performing the connection/disconnection of a signal line that connects a semiconductor relay with a receiver and a transmission driver when an output of a data output inhibit circuit is on. SOLUTION: As power VCC is fed, a data transmission inhibit signal becomes a higher level, a circuit (203) is turned on at certain voltage. The data transmission inhibit signal is on a low level and a power supply unit 120 is not turned on until power VCC voltage becomes stable. Even if the data transmission inhibit signal 101 becomes on at that time, a circuit (207) is prevented from being turned on because a signal line becomes a low level due to a circuit (203). A timing circuit makes the timing in which a semiconductor relay 106 is turned on delayed more than a semiconductor relay 105 and the relay 106 disconnects a signal line 109 even in a transient state when power supply is turned on/off by a transmission driver by making off timing early.

6. 发明专利

JPH11327941A DUPLEX COMPUTER SYSTEM 失效
公开(公告)号：JPH11327941A
公开(公告)日：1999-11-30
申请号：JP12910198
申请日：1998-05-12
申请人： HITACHI LTD
发明人： HIUGA KAZUHIRO , MIYAZAKI YOSHIHIRO , YOSHIDA KOKI
IPC分类号： G06F11/18 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable duplex computer system using a data output device not provided with a hardware for clock synchronization for performing data output in a fixed time of about several tens μ seconds without the need of control by a user program. SOLUTION: This system is provided with duplexed processor devices 100 (100A and 100B), duplexed data output devices 300 (300A and 300B), input/output buses 210 (210A and 210B) for connecting them, input/output bus controllers 200 (200A and 200B) and data selectors 400 (400A and 400B) for selecting the data of the duplexed data output devices. The respective data output devices 300 are provided with two connection ports for the data output so as to distribute and output the same data to the duplexed respective data selectors 400. Thus, the highly reliable data output device using the data output device not provided with the hardware for the clock synchronization for performing the data output in a fixed time of about several tens μ seconds without the need of the control by the user program can be provided.

7. 发明专利

JPH08190494A HIGH-RELIABILITY COMPUTER WITH DUAL PROCESSORS 失效
公开(公告)号：JPH08190494A
公开(公告)日：1996-07-23
申请号：JP239095
申请日：1995-01-11
申请人： HITACHI LTD
发明人： YAMAGUCHI SHINICHIRO , NAKAMIGAWA TETSUAKI , MIYAZAKI NAOTO , MIYAZAKI YOSHIHIRO , HIUGA KAZUHIRO , ISHIKAWA SUKETAKA , OGURO HIROSHI
IPC分类号： G06F11/18
摘要： PURPOSE: To provide a high-reliability computer which is highly common with general-purpose computers and also high in performance-cost ratio. CONSTITUTION: The computer consisting of two CPUs 1A and 1B of the same constitution and an input/output device has an identical-frequency, in-phase clock supply means for both the CPUs 1A and 1B, a doubled controller DSBA 2 which connects both the CPU 1A and 1B to the input/output device, and a communication means which sends and receives the states of the CPUs, etc., between both the CPUs 1A and 1B. The DSBA 2 selects an output instruction from one CPU and sends it to the input/output device, sends a response from the input/output device to both the CPUs 1A and 1B, informs the memories in the CPUs 1A and 1B of memory access from the an input/output device, and selects a memory access response from one CPU and sends it to the input/ output device. If a fault occurs in the CPU 1A or 1B, the DSBA 2 automatically disconnects the faulty CPU and continues to execute a program with the sound CPU. Consequently, high reliability is easily obtained at a low cost and a fault position can be replaced during on-line transaction execution.

8. 发明专利

JP2003203189A COMPUTER SYSTEM AND RENTAL METHOD 审中-公开
公开(公告)号：JP2003203189A
公开(公告)日：2003-07-18
申请号：JP2002000754
申请日：2002-01-07
申请人： HITACHI LTD
发明人： HIUGA KAZUHIRO
IPC分类号： G06Q30/04 , G06Q30/06 , G06Q50/00 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To account a rental charge according to operating time in a computer system having a rental server. SOLUTION: A user system 100 and a remote monitoring center 200 are connected by a wide area network 300, and a use requesting telegram from a maintenance console 150 is received by the remote monitoring center 200 together with a server device. Server ID included in the use requesting telegram is actual server ID and virtual server ID, and the latter is used for a use request of the rental server. A monitor 210 converts the virtual server ID into the actual server ID, and transmits the ID to the server device. The server device executes rising processing on a server when the received server ID coincides with one's own server ID. The remote monitoring center 200 accounts by measuring the operating time of the server device with every user with converted ID-received time as the origin. COPYRIGHT: (C)2003,JPO

9. 发明专利

JP2000207291A METHOD FOR DIAGNOSING MEMORY DEVICE 失效
公开(公告)号：JP2000207291A
公开(公告)日：2000-07-28
申请号：JP609199
申请日：1999-01-13
申请人： HITACHI LTD
发明人： HIUGA KAZUHIRO , FUKUMARU HIROAKI
IPC分类号： G06F12/16 , G06F11/34 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To obtain a method for diagnosing the fault of a memory element by referring to a memory address where single-bit error occurrence is recorded and deciding that a control circuit in a memory element has gone out of order, when the memory addresses for single-bit errors generated in a prescribed time are more than a prescribed number. SOLUTION: When the type of the latest error in an error log file is '01', a memory error file is referred to (30). The memory address of the last error log in the memory error file is compared with the memory address of the latest error (40), and when the addresses do not match each other, the current number of memory addresses is compared with a previously set prescribed value (60). When prescribed value is exceeded, it is decided that the control circuit of the memory element is out of order (70) on condition that the generation time difference between the oldest error log and the latest error log in the memory error file is within the previously set prescribed time, thereby outputting an alarm (80). Then all the error logs in the memory error file are erased (90).

10. 发明专利

JPH09134334A INTER-MULTIPROCESSOR SYNCHRONIZING PROCESSING CONTROLLING METHOD, MULTIPROCESSOR SYSTEM AND FAULT TOLERANT SYSTEM 失效
公开(公告)号：JPH09134334A
公开(公告)日：1997-05-20
申请号：JP29289595
申请日：1995-11-10
申请人： HITACHI LTD , HITACHI INF & CONTROL SYST
发明人： NAKANIWA KAZUHIRO , KAYUKAWA SATORU , HAGITANI SADAO , MIYAZAKI YOSHIHIRO , HIUGA KAZUHIRO , EBARA OSAMU
IPC分类号： G06F15/16
摘要： PROBLEM TO BE SOLVED: To synchronously execute the same processing between plural processing units without increasing the processing load of an operating system. SOLUTION: At the time of outputting start requests for reading out various state information from respective processors 3, 4, processing units 1, 2 respectively collect and enter various state information from the other processing units 2, 1 at the same time through synchronous transmitting/receiving data buses 13, 14 in addition to the state information of their own processing units. State information reedited to a prescribed format common to all the processing units are returned to the processors 3, 4 at the same timing together with the various state information of their own processing units.

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