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1. 发明专利

JP2013239722A Conductive base material for plating, method for producing the same, method for producing base material with conductor layer pattern using the method, base material with conductor layer pattern, and translucent electromagnetic wave shielding member 有权
标题翻译：用于制造导电基材的方法，用于制造其方法，使用该方法的导体层图案生产基体材料的方法，具有导体层模式的基底材料和透明电磁波屏蔽构件
公开(公告)号：JP2013239722A
公开(公告)日：2013-11-28
申请号：JP2013136633
申请日：2013-06-28
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： NAOYUKI SUSUMU , SUZUKI KYOSUKE , TOSAKA MINORU
IPC分类号： H05K9/00 , G09F9/00
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a conductive base material for plating, by which a base material with a conductor pattern patterned so as to have conductivity and light transmitting property can be produced at high productivity by using a transfer method, while, furthermore, the conductive base material for plating can be easily prepared.SOLUTION: A method for producing a conductive base material for plating includes the steps of: (A) forming a removable protruded pattern (6) on the surface of a conductive base material (2); (B) forming an insulation layer (7) made of diamond-like carbon (DLC) or an inorganic material on the surface of the conductive base material on which the removable protruded pattern is formed; and (C) removing the protruded pattern to which the insulation layer is attached.
摘要翻译：要解决的问题：提供一种用于制造用于电镀的导电基材的方法，通过该方法可以通过使用转印方法以高生产率制造具有图案化以具有导电性和透光性的导体图案的基材，同时此外，可以容易地制备用于电镀的导电基材。解决方案：一种用于电镀的导电基材的制造方法，包括以下步骤：（A）在导电性基材的表面上形成可移除的突出图案（6）（2）; （B）在其上形成有可移除的突出图案的导电基材的表面上形成由类金刚石碳（DLC）制成的绝缘层（7）或无机材料; 和（C）去除附着有绝缘层的突出图案。

2. 发明专利

JP2015041692A 配線基板およびその製造方法审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：JP2015041692A
公开(公告)日：2015-03-02
申请号：JP2013171747
申请日：2013-08-21
申请人：日立化成株式会社 , Hitachi Chemical Co Ltd
发明人： NAOYUKI SUSUMU , TATENO KIICHI , INADA TEIICHI , HIROYAMA YUKIHISA
IPC分类号： H05K1/02 , H01L23/12 , H05K3/00
摘要：【課題】薄型化可能であり、優れたフレキシブル性を有する配線基板およびその製造方法を提供する。【解決手段】本発明の配線基板(1)は、第1の主面(22)、第2の主面(24)および側面(24)を有しパターン状に形成された金属層(20)と金属層(20)の周囲に配置された第1の絶縁層(30)とからなる基材部(10)、金属層(20)の第1の主面(22)を覆う第2の絶縁層(30)、および金属層(20)の第2の主面(24)を覆う第3の絶縁層(50)を含む。【選択図】図2
摘要翻译：要解决的问题：提供可以变薄并且具有良好柔性的布线板及其制造方法。解决方案：布线板（1）包含由金属层（20）构成的基材部分（10））具有第一主表面（22），第二主表面（24）和侧表面（24）并形成为图案形状;以及布置在金属层（20）周围的第一绝缘层（30）覆盖金属层（20）的第一主表面（22）的第二绝缘层（30）; 和覆盖金属层（20）和第二主表面（24）的第三绝缘层（50）。

3. 发明专利

JP2014116458A Member for mounting semiconductor element and semiconductor device using the same 审中-公开
标题翻译：用于安装半导体元件和使用其的半导体器件的部件
公开(公告)号：JP2014116458A
公开(公告)日：2014-06-26
申请号：JP2012269339
申请日：2012-12-10
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： NAOYUKI SUSUMU , INADA TEIICHI , TATENO KIICHI
IPC分类号： H01L23/12
CPC分类号： H01L24/97 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01322 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a member for mounting a semiconductor element capable of reducing the number of steps, the number of components, and the cost, and a semiconductor device using the same.SOLUTION: There is provided a member 10 for mounting a semiconductor element, comprising: a carrier medium 37 including a base medium 11 and an adhesive layer 12; and a conductive metal layer pattern 14 precipitated by an electrolytic coating. The conductive metal layer pattern 14 is adhered to the base medium 11 via the adhesive layer 12. The conductive metal layer pattern 14 is shaped so as to include a convex portion 19 in a mount shape including an approximately flat surface.
摘要翻译：要解决的问题：提供一种用于安装能够减少台阶数，部件数量和成本的半导体元件的部件，以及使用其的半导体器件。解决方案：提供一种用于安装半导体元件，包括：载体介质37，其包括基底介质11和粘合剂层12; 以及通过电解涂层沉淀的导电金属层图案14。导电性金属层图案14经由粘合剂层12粘附到基底介质11.导电金属层图案14成形为包括具有大致平坦表面的安装形状的凸部19。

4. 发明专利

JP2015041693A 多層配線基板およびその製造方法ならびに積層コイル部品审中-公开
标题翻译：多层布线板及其制造方法和层叠线圈组件
公开(公告)号：JP2015041693A
公开(公告)日：2015-03-02
申请号：JP2013171748
申请日：2013-08-21
申请人：日立化成株式会社 , Hitachi Chemical Co Ltd
发明人： NAOYUKI SUSUMU , TATENO KIICHI , INADA TEIICHI , HIROYAMA YUKIHISA
IPC分类号： H05K3/46 , H05K1/16 , H05K3/20 , H05K3/28
摘要：【課題】薄型化が可能であり、生産性に優れた多層配線基板およびその製造方法を提供する。また、薄型化が可能であり、生産性に優れた積層コイル部品を提供する。【解決手段】本発明の多層配線基板は、複数の配線層(1)を積層してなる多層配線基板であって、複数の配線層のうち、少なくとも1層の配線層(1)が、第1の主面(22)、第2の主面(24)および側面(26)を有しパターン状に形成された金属層(20)と金属層(20)の周囲に配置された第1の絶縁層(30)とからなる基材部(10)、金属層(20)の第1の主面(22)を覆う第2の絶縁層(40)、および金属層(20)の第2の主面(24)を覆う第3の絶縁層(50)を含み、金属層(20)の第1の主面(22)の一部は、第2の絶縁層(40)から露出し、金属層(20)の第2の主面(24)の一部は、第3の絶縁層(50)から露出している。【選択図】図3
摘要翻译：要解决的问题：提供可以变薄并且生产率高的多层布线板及其制造方法，并提供可以变薄并且生产率高的层叠线圈组件。解决方案：多层布线板是层叠有多个布线层（1）的多层布线基板，所述多个布线层中的至少一个布线层（1）包含由具有第一主体（1）的金属层（20）构成的基材部（10）表面（22），第二主表面（24）和侧表面（26）并形成图案形状;以及布置在金属层（20）周围的第一绝缘层（30）覆盖金属层（20）的第一主表面（22）的第二绝缘层（40）; 以及覆盖金属层（20）的第二主表面（24）的第三绝缘层（50）。金属层（20）的第一主表面（22）的一部分从第二绝缘层（40）露出，金属层（20）的第二主表面（24）的一部分从第三绝缘层绝缘层（50）。

5. 发明专利

JP2014125652A Method for manufacturing metal filter 有权
标题翻译：制造金属过滤器的方法
公开(公告)号：JP2014125652A
公开(公告)日：2014-07-07
申请号：JP2012283158
申请日：2012-12-26
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： SUZUKI TAKAHIRO , NAOYUKI SUSUMU , UEHARA TOSHISHIGE , KIKUHARA YOSHIHITO
IPC分类号： C25D1/08 , C12M1/00 , C12M1/12 , C12M3/06 , G03F7/40
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a metal filter having no burrs on a hole inner wall of a through-hole and high process accuracy of a hole diameter of the through-hole.SOLUTION: The method for manufacturing a metal filter comprises: a deposition step of depositing a layer of a photosensitive resin on a copper substrate; an exposure step of exposing a predetermined part of the photosensitive resin layer; a development step of forming a resist pattern comprising a cured product of the photosensitive resin by developing the photosensitive resin; a first plating step of forming a first plating layer by subjecting the copper substrate with the resist pattern formed thereon to metal plating; a second plating step of forming a second plating layer by subjecting the copper substrate having the resist pattern and the first plating layer formed thereon to metal plating with a metal different from the metal of the first plating layer; a dissolution step of obtaining a structure composed of the resist pattern and the second plating layer by removing the copper substrate and the first plating layer by chemical dissolution; and a stripping step of obtaining the second plating layer by removing the resist pattern from the structure. The second plating layer serves as the metal filter.
摘要翻译：要解决的问题：提供一种用于制造在通孔的孔内壁上没有毛刺的金属过滤器的方法，并且通孔的孔径的加工精度高。解决方案：金属过滤器的制造方法包括：在铜基板上沉积感光树脂层的沉积步骤; 曝光步骤，曝光所述感光性树脂层的预定部分; 通过显影感光性树脂形成包含感光性树脂的固化物的抗蚀剂图案的显影工序; 第一电镀步骤，通过使铜基板与其上形成的抗蚀剂图案进行金属镀覆来形成第一镀层; 第二电镀步骤，通过使形成有抗蚀剂图案的铜基板和形成在其上的第一镀层的铜基板与不同于第一镀层的金属的金属进行金属镀覆来形成第二镀层; 溶解步骤，通过化学溶解除去铜基材和第一镀层，得到由抗蚀剂图案和第二镀层组成的结构; 以及通过从结构中去除抗蚀剂图案来获得第二镀层的剥离步骤。第二镀层用作金属过滤器。

6. 发明专利

JP2013182895A Member for mounting semiconductor element and semiconductor device using the same 审中-公开
标题翻译：用于安装半导体元件和使用其的半导体器件的部件
公开(公告)号：JP2013182895A
公开(公告)日：2013-09-12
申请号：JP2012043444
申请日：2012-02-29
申请人： Hitachi Chemical Co Ltd , 日立化成株式会社
发明人： NAOYUKI SUSUMU , INADA TEIICHI , TATENO KIICHI
IPC分类号： H01L23/12 , H01L23/08 , H01L23/28
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a member for mounting a semiconductor element which solves problems that when the size of an exposed part of a metal layer, on which a semiconductor element is mounted, becomes smaller than the size of the element due to the downsizing of a package, an insulation part of a pattern peripheral part blocks normal connection between the element and the metal layer or a capillary of a bonding device contacts with the insulation part and inhibits the wire connection during the wire bonding, and to provide a semiconductor device using the member for mounting the semiconductor element.SOLUTION: A member for mounting a semiconductor element includes a first conductive metal layer pattern and an insulation part on a carrier substrate. The first conductive metal layer pattern is covered by the insulation part in at least its peripheral part so as to have a partial exposed part, and a second metal layer is provided on an exposed surface of the first conductive metal layer pattern. A height of a surface of the second metal layer is equal to or higher than a height of the insulation part covering the peripheral part.
摘要翻译：要解决的问题：提供一种用于安装半导体元件的部件，其解决了当安装有半导体元件的金属层的暴露部分的尺寸变得小于由于尺寸小的元件的尺寸封装的图案周边部分的绝缘部分阻挡元件和金属层之间的正常连接，或者接合装置的毛细管与绝缘部件接触并且在引线接合期间阻止电线连接，并且提供半导体器件使用用于安装半导体元件的部件。解决方案：用于安装半导体元件的部件包括第一导电金属层图案和载体基板上的绝缘部分。第一导电金属层图案至少在其周边部分被绝缘部件覆盖以具有部分暴露部分，并且第二金属层设置在第一导电金属层图案的暴露表面上。第二金属层的表面的高度等于或高于覆盖周边部分的绝缘部分的高度。

7. 发明专利

HK1027215A1 Broad for mounting semiconductor element, method for manufacturing the same, and semiconductor device 未知
公开(公告)号：HK1027215A1
公开(公告)日：2001-01-05
申请号：HK00106137
申请日：2000-09-27
申请人： HITACHI CHEMICAL CO LTD
发明人： FUKUTOMI NAOKI , WAKASHIMA YOSHIAKI , NAOYUKI SUSUMU , KIDA AKINARI
IPC分类号： H01L20060101 , H01L21/48 , H01L21/60 , H01L23/13 , H01L23/24 , H01L23/31 , H01L23/36 , H01L23/498 , H01L29/06 , H05K3/00
摘要： A semiconductor device comprising a substrate with a cavity portion for mounting a semiconductor chip is provided to achieve a high reliability and to decrease a size and a fabricating cost. The cavity portion capable of mounting the semiconductor chip (1) at the center portion of the substrate is formed by press forming with a projected portion (13a) of a die (13) while adhering a press shapeable wiring body comprising a copper wiring (12) which becomes wiring material, a barrier layer (11) such as nickel alloy or the like, and a copper foil (10) which is a carrier layer, to a plastic substrate (14,15), so as to have wiring (2) buried into a surface of the substrate and to form a ramp between an inner connection terminal portion connecting to the semiconductor chip (1) and an external connection terminal portion connecting to an external connection terminals (5), the internal and external connection terminal portions being two edge portions of the wiring (2).

8. 发明专利

AU7082798A Board for mounting semiconductor element, method for manufacturing the same, andsemiconductor device 未知
公开(公告)号：AU7082798A
公开(公告)日：1998-11-24
申请号：AU7082798
申请日：1998-04-30
申请人： HITACHI CHEMICAL CO LTD
发明人： FUKUTOMI NAOKI , WAKASHIMA YOSHIAKI , NAOYUKI SUSUMU , KIDA AKINARI
IPC分类号： H01L21/48 , H01L21/60 , H01L23/13 , H01L23/24 , H01L23/31 , H01L23/36 , H01L23/498 , H01L29/06 , H05K3/00 , H01L23/12
摘要： A semiconductor device comprising a substrate with a cavity portion for mounting a semiconductor chip is provided to achieve a high reliability and to decrease a size and a fabricating cost. The cavity portion capable of mounting the semiconductor chip (1) at the center portion of the substrate is formed by press forming with a projected portion (13a) of a die (13) while adhering a press shapeable wiring body comprising a copper wiring (12) which becomes wiring material, a barrier layer (11) such as nickel alloy or the like, and a copper foil (10) which is a carrier layer, to a plastic substrate (14,15), so as to have wiring (2) buried into a surface of the substrate and to form a ramp between an inner connection terminal portion connecting to the semiconductor chip (1) and an external connection terminal portion connecting to an external connection terminals (5), the internal and external connection terminal portions being two edge portions of the wiring (2).

9. 发明专利

DE2838241A1 未知
公开(公告)号：DE2838241A1
公开(公告)日：1979-03-08
申请号：DE2838241
申请日：1978-09-01
申请人： HITACHI CHEMICAL CO LTD
发明人： FUKUTOMI NAOKI , TSURU YOSHIYUKI , KAWAGUCHI KUNIO , NAOYUKI SUSUMU
IPC分类号： G03G15/05 , B41J2/395 , G01D15/06 , G11B11/08 , H04N1/24
摘要： A multistylus head device which comprises a vast plurality of insulated wires embedded in an insulating substrate having through-holes. The present multistylus device is characterized in that the insulated wires have their respective free terminals exposed on one edge of said insulating substrate and disposed in parallel at predetermined equal intervals in close proximity to each other to form electrodes and have their other terminals exposed respectively on the inner walls of said through-holes; and said other exposed terminals of the insulated wires are connected respectively to metal layers electrolessly deposited on the inner walls of the through-holes. The present multistylus head device is compact in size and excellent in reliability of terminal connection and is capable of recording a transmitted information with high density of printing. The exposed disposition of the wires at their respective free terminals in a parallel state at predetermined equal intervals are skillfully realized according to the method of the present invention. Thus, the present device can be produced at low cost, with reliability of the function of the produced device and is suitable for mass-production.

10. 发明公开

EP2098362A4 ENGRAVED PLATE AND BASE MATERIAL HAVING CONDUCTOR LAYER PATTERN USING THE ENGRAVED PLATE 审中-公开
标题翻译：刻了盘和母材LEITSCHICHTSTRUKTUR和刻碟
公开(公告)号：EP2098362A4
公开(公告)日：2012-07-18
申请号：EP07860426
申请日：2007-12-27
申请人： HITACHI CHEMICAL CO LTD
发明人： NAOYUKI SUSUMU , KANBARA HISASHIGE , TOSAKA MINORU , SUZUKI KYOSUKE , OKAMURA TOSHIROU , KIKUHARA YOSHIHITO , NEGISHI MASAMI , FUJIEDA TADAYASU , TSUYAMA KOUICHI
IPC分类号： B32B3/14 , B32B3/30 , B32B9/00 , B32B15/00 , B41C1/00 , B41N1/06 , B41N1/12 , C25D1/00 , C25D5/02 , H05K9/00
CPC分类号： B41N1/06 , B41C1/00 , B41N1/12 , C25D1/00 , C25D1/006 , H05K3/205 , H05K9/0096 , H05K2201/09827 , Y10T428/2457 , Y10T428/24612 , Y10T428/2462 , Y10T428/30

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