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    • 2. 发明授权
    • VSB demodulator
    • VSB解调器
    • US06067329A
    • 2000-05-23
    • US866885
    • 1997-05-30
    • Hisaya KatoSeiji SakashitaKunio Ninomiya
    • Hisaya KatoSeiji SakashitaKunio Ninomiya
    • H04L27/06H04L27/22
    • H04L27/06
    • A Vestigal Sideband (VSB) demodulator having a clock generator for generating a clock signal based on a symbol frequency of the VSB signal; an A/D converter for converting the VSB signal into a digital signal based on the clock signal of the clock generator; a first multiplier for multiplying the digital signal by a first value sequence and generating a first multiplier output signal; a second multiplier for multiplying the digital signal by a second value sequence and generating a second multiplier output signal; a complex type filter for shaping and VSB demodulation of the multiplier output signals and generating Inphase and Quadrature data output signals; a decimating circuit for decimating the Inphase and Quadrature data output signals and generating decimated signals; a complex multiplier for multiplying the decimated signals by a predetermined value and generating multiplied output signals; an error detector for detecting a frequency deviation and a phase deviation from the multiplied output signals and generating the predetermined value for the complex multiplier; and DC offset canceler for removing a DC component from a portion of the multiplied output signals of the complex multiplier.
    • 一种Vestigal边带(VSB)解调器,具有时钟发生器,用于根据VSB信号的符号频率产生时钟信号; A / D转换器,用于基于时钟发生器的时钟信号将VSB信号转换成数字信号; 第一乘法器,用于将数字信号乘以第一值序列并产生第一乘法器输出信号; 第二乘法器,用于将数字信号乘以第二值序列并产生第二乘法器输出信号; 用于整形和VSB解调乘法器输出信号并产生同相和正交数据输出信号的复合型滤波器; 抽取电路,用于抽取同相和正交数据输出信号并产生抽取信号; 复数乘法器,用于将抽取的信号乘以预定值并产生相乘的输出信号; 误差检测器,用于检测来自相乘的输出信号的频率偏差和相位偏差,并产生复数乘法器的预定值; 以及DC偏移消除器,用于从复数乘法器的相乘输出信号的一部分中去除DC分量。