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1. 发明授权

US07573128B2 Semiconductor module in which a semiconductor package is bonded on a mount substrate 有权
标题翻译：半导体封装结合在安装基板上的半导体模块
公开(公告)号：US07573128B2
公开(公告)日：2009-08-11
申请号：US10836098
申请日：2004-04-29
申请人： Hisashi Tanie , Nae Hisano , Koji Hosokawa
发明人： Hisashi Tanie , Nae Hisano , Koji Hosokawa
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L2224/50 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/01047 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/3011 , H01L2924/3511 , H01L2924/00 , H01L2924/01005
摘要： A semiconductor module comprises: semiconductor packages each comprising a semiconductor element, a wiring substrate having a wiring member connected to the semiconductor element and external terminals connected to the wiring member, and a first organic film formed on a side of the semiconductor element opposed to a side toward the wiring substrate; and a mount substrate, on which the semiconductor element is mounted. First of the semiconductor packages and second of the semiconductor packages are stacked. Second organic films are provided between the wiring substrate of the first semiconductor package and the first organic film of the second semiconductor package and between the mount substrate and the semiconductor package.
摘要翻译：半导体模块包括：各自包括半导体元件的半导体封装，具有连接到半导体元件的布线构件的布线基板和连接到布线构件的外部端子，以及形成在与半导体元件相对的半导体元件的一侧上的第一有机膜一侧朝向布线基板; 以及安装基板，其上安装有半导体元件。第一半导体封装和第二半导体封装堆叠。第二有机膜设置在第一半导体封装的布线基板和第二半导体封装的第一有机膜之间以及安装基板和半导体封装之间。

2. 发明申请

US20050001302A1 Semiconductor module 有权
标题翻译：半导体模块
公开(公告)号：US20050001302A1
公开(公告)日：2005-01-06
申请号：US10836098
申请日：2004-04-29
申请人： Hisashi Tanie , Nae Hisano , Koji Hosokawa
发明人： Hisashi Tanie , Nae Hisano , Koji Hosokawa
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07 , H01L25/10 , H01L23/02
CPC分类号： H01L25/105 , H01L2224/50 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/01047 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/3011 , H01L2924/3511 , H01L2924/00 , H01L2924/01005
摘要： A semiconductor module comprises: semiconductor packages each comprising a semiconductor element, a wiring substrate having a wiring member connected to the semiconductor element and external terminals connected to the wiring member, and a first organic film formed on a side of the semiconductor element opposed to a side toward the wiring substrate; and a mount substrate, on which the semiconductor element is mounted. First of the semiconductor packages and second of the semiconductor packages are stacked. Second organic films are provided between the wiring substrate of the first semiconductor package and the first organic film of the second semiconductor package and between the mount substrate and the semiconductor package.
摘要翻译：半导体模块包括：各自包括半导体元件的半导体封装，具有连接到半导体元件的布线构件的布线基板和连接到布线构件的外部端子，以及形成在与半导体元件相对的半导体元件的一侧上的第一有机膜一侧朝向布线基板; 以及安装基板，其上安装有半导体元件。第一半导体封装和第二半导体封装堆叠。第二有机膜设置在第一半导体封装的布线基板和第二半导体封装的第一有机膜之间以及安装基板和半导体封装之间。

3. 发明申请

US20050230824A1 BGA semiconductor device having a dummy bump 有权
标题翻译： BGA半导体器件具有虚拟凸块
公开(公告)号：US20050230824A1
公开(公告)日：2005-10-20
申请号：US11105546
申请日：2005-04-14
申请人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
发明人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
IPC分类号： H01L23/12 , H01L21/60 , H01L23/31 , H01L23/48 , H01L23/498 , H05K3/30 , H05K3/34
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.
摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

4. 发明授权

US07659623B2 Semiconductor device having improved wiring 有权
标题翻译：具有改进布线的半导体器件
公开(公告)号：US07659623B2
公开(公告)日：2010-02-09
申请号：US11815084
申请日：2006-04-07
申请人： Yuji Watanabe , Koji Hosokawa , Hisashi Tanie
发明人： Yuji Watanabe , Koji Hosokawa , Hisashi Tanie
IPC分类号： H01L23/488 , H01L23/48 , H01L25/07 , H01L23/12 , H01L25/065 , H01L25/18
CPC分类号： H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L25/105 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2924/1461 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/3511 , H01L2924/00
摘要： An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.
摘要翻译：提供了能够防止表层布线的应力集中区域的布线断裂的半导体装置等电子部件。在设置有支撑球（5）的半导体装置中，在支撑球（5）附近的区域（7（A））和末端的区域（7（B））中不形成普通的布线的面向支撑球（5）的半导体芯片，其是封装衬底（2）的应力集中区域。相反，布线（6（C））远离这些区域形成，或者在这些区域中形成宽布线。

5. 发明授权

US08164186B2 BGA semiconductor device having a dummy bump 有权
标题翻译： BGA半导体器件具有虚拟凸块
公开(公告)号：US08164186B2
公开(公告)日：2012-04-24
申请号：US11105546
申请日：2005-04-14
申请人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
发明人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.
摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

6. 发明申请

US20100295179A1 BGA SEMICONDUCTOR DEVICE HAVING A DUMMY BUMP 失效
标题翻译：具有DUMMY BUMP的BGA半导体器件
公开(公告)号：US20100295179A1
公开(公告)日：2010-11-25
申请号：US12846120
申请日：2010-07-29
申请人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
发明人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
IPC分类号： H01L23/498
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.
摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

7. 发明授权

US08222737B2 BGA semiconductor device having a dummy bump 失效
公开(公告)号：US08222737B2
公开(公告)日：2012-07-17
申请号：US12846120
申请日：2010-07-29
申请人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
发明人： Yuji Watanabe , Hisashi Tanie , Koji Hosokawa , Mitsuaki Katagiri , Ichiro Anjo
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/81 , H01L2224/81801 , H01L2924/15311 , H05K3/303 , H05K3/3436 , H05K2201/09781 , H05K2201/2036 , Y02P70/613
摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

8. 发明申请

US20080150115A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20080150115A1
公开(公告)日：2008-06-26
申请号：US11815084
申请日：2006-04-07
申请人： Yuji Watanabe , Koji Hosokawa , Hisashi Tanie
发明人： Yuji Watanabe , Koji Hosokawa , Hisashi Tanie
IPC分类号： H01L23/488
CPC分类号： H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L25/105 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2924/1461 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/3511 , H01L2924/00
摘要： An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.
摘要翻译：提供了能够防止表层布线的应力集中区域的布线断裂的半导体装置等电子部件。在设置有支撑球（5）的半导体装置中，在支撑球（5）附近的区域（7（A））和末端的区域（7（B））中不形成普通的布线的面向支撑球（5）的半导体芯片，其是封装衬底（2）的应力集中区域。相反，布线（6（C））远离这些区域形成，或者在这些区域中形成宽布线。

9. 发明授权

US08873247B2 Device and manufacturing method of the same 有权
标题翻译：装置及制造方法相同
公开(公告)号：US08873247B2
公开(公告)日：2014-10-28
申请号：US13181040
申请日：2011-07-12
申请人： Koji Hosokawa
发明人： Koji Hosokawa
IPC分类号： H05K7/00 , H01L21/56 , H01L23/31 , H01L23/00 , H05K3/28 , H05K3/00
CPC分类号： H01L21/565 , H01L21/561 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/49171 , H01L2224/73265 , H01L2224/83192 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H05K3/0052 , H05K3/0097 , H05K3/284 , H05K2203/1327 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A device includes a wiring board, an element mounted on the wiring board, a spacer member intervening between the wiring board and the element to form a space therebetween, and an encapsulation body filling the space and encapsulating the element on the wiring board.
摘要翻译：一种器件包括布线板，安装在布线板上的元件，插入在布线板和元件之间以形成间隔的间隔件，以及填充该空间并将元件封装在布线板上的封装体。

10. 发明授权

US5732042A Dram array with local latches 失效
标题翻译： Dram阵列与本地锁存器
公开(公告)号：US5732042A
公开(公告)日：1998-03-24
申请号：US743953
申请日：1996-10-29
申请人： Toshio Sunaga , Koji Hosokawa
发明人： Toshio Sunaga , Koji Hosokawa
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/10 , G11C7/1006 , G11C7/1051
摘要： A DRAM array has a row decoder means 2 and a column decoder 3 which are connected to a word line and a bit line of a cell matrix portion, respectively. The column decoder means 3 comprises a plurality of bit switches 44 and 46 for connecting a predetermined bit line to an output bus. Local latches 36 store data bits, each of the local latches provide for one group of bit lines 32 which is a unit of predetermined number of bit lines. The bit switches are arranged in a hierarchical structure, and connection between the bit line and the output bus is attained by two bit switches connected in series thereby load capacitance on the data lines 52 and 56 being able to be reduced. Data in respective local latches 36 is stored in the local buffer 74 in a predetermined order so that it can be burst transferred at a high speed.
摘要翻译： DRAM阵列具有分别连接到单元矩阵部分的字线和位线的行解码器装置2和列解码器3。列解码器装置3包括用于将预定位线连接到输出总线的多个位开关44和46。本地锁存器36存储数据位，每个本地锁存器提供一组位线32，位线32是预定数量的位线的单位。位开关以分层结构布置，并且通过串联连接的两位开关来实现位线和输出总线之间的连接，从而可以减少数据线52和56上的电容。各个本地锁存器36中的数据以预定顺序存储在本地缓冲器74中，使得其可以以高速突发传送。

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