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1. 发明授权

US06183920B2 Semiconductor device geometrical pattern correction process and geometrical pattern extraction process 失效
标题翻译：半导体器件几何图案校正过程和几何图案提取过程
公开(公告)号：US06183920B2
公开(公告)日：2001-02-06
申请号：US09348316
申请日：1999-07-07
申请人： Hiroyuki Tsujikawa , Hidenori Shibata , Kiyohito Mukai
发明人： Hiroyuki Tsujikawa , Hidenori Shibata , Kiyohito Mukai
IPC分类号： G03F900
CPC分类号： G03F7/70441 , G03F1/36
摘要： A semiconductor device geometrical pattern correction process, semiconductor device manufacturing process and geometrical pattern extraction process are provided, which make it possible to eliminate the adverse effect of corner rounding accompanying miniaturization, that is, a decrease in the projection amount of a gate, while avoiding increased chip area. The correction process comprises a step 102 of detecting a concave diffusion layer corresponding portion and a step 103 of correcting either the concave diffusion layer corresponding portion or a transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion in order to ensure the projection of the gate from the concave diffusion layer corresponding portion against possible corner rounding.
摘要翻译：提供半导体器件几何图案校正处理，半导体器件制造工艺和几何图案提取处理，这可以消除伴随着小型化的圆角倒圆的不良影响，即，避免浇口的投影量的减少，同时避免增加芯片面积。校正处理包括检测凹面扩散层对应部分的步骤102和校正从凹形扩散层对应部分突出的凹形扩散层对应部分或晶体管栅极对应部分的步骤103，以确保投影来自凹面扩散层的对应部分的栅极可能围绕可能的角落四舍五入。

2. 发明授权

US06303251B1 Mask pattern correction process, photomask and semiconductor integrated circuit device 失效
标题翻译：掩模图案校正工艺，光掩模和半导体集成电路器件
公开(公告)号：US06303251B1
公开(公告)日：2001-10-16
申请号：US09360989
申请日：1999-07-27
申请人： Kiyohito Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
发明人： Kiyohito Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
IPC分类号： G03F900
CPC分类号： G03F7/70441 , G03F1/36
摘要： In order that CAD processing time required for modifying an input design pattern to compensate for optical proximity effects is reduced, increases in the number of base shapes when corrected data are converted into EB data are restricted, and false detection of defects in a photomask inspection process is restricted, the following steps are taken. At a shape selection step, rectangular shapes are divided into a dense rectangular shape group and a non-dense rectangular shape group according to the distance of each rectangular shape to an adjacent rectangular shape. At a number-of-shapeas comparison step, the number of shapes included in the dense rectangular shape group is compared to the number of shapes included in the non-dense rectangular shape group to select either shape group for correction. At a correction process selection step, a correction process suited for the selected shape group is selected. At a shape correction step, optical proximity correction is made. At a shape combining step, a group of corrected shapes and the rectangular shape group different from the selected one are combined.
摘要翻译：为了减少修改输入设计图案以补偿光学邻近效应所需的CAD处理时间，校正数据被转换为EB数据时的基本形状数量的增加受到限制，并且光掩模检查过程中的缺陷的错误检测被限制，采取以下步骤。在形状选择步骤中，矩形形状根据每个矩形形状与相邻矩形形状的距离被分成致密矩形形状组和非密集矩形形状组。在数字形状比较步骤中，将包含在密集矩形形状组中的形状的数量与包括在非致密矩形形状组中的形状的数量进行比较，以选择用于校正的形状组。在校正处理选择步骤中，选择适合所选择的形状组的校正处理。在形状校正步骤中，进行光学邻近校正。在形状组合步骤中，组合一组校正形状和与所选择的形状组不同的矩形形状组合。

3. 发明申请

US20050224914A1 Semiconductor integrated circuit device, method of enerating pattern thereof, method of manufacturing the same, and pattern generating apparatus for the same 审中-公开
标题翻译：半导体集成电路装置及其图案的制造方法，制造方法以及图案生成装置
公开(公告)号：US20050224914A1
公开(公告)日：2005-10-13
申请号：US11103490
申请日：2005-04-12
申请人： Kiyohito Mukai , Hiroyuki Tsujikawa
发明人： Kiyohito Mukai , Hiroyuki Tsujikawa
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/04 , H01L27/08 , H01L31/0392
CPC分类号： H01L23/5223 , H01L23/5286 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： To provide a semiconductor integrated circuit device capable of effectively absorbing power supply noise, of achieving the stable operation of a circuit, and particularly, of absorbing noise in a vicinity of a noise generating source. The semiconductor integrated circuit device has at least one circuit block. The semiconductor integrated circuit device includes a bypass capacitor having a first conductor layer 1a formed on the circuit block and a second conductor layer 1b formed on the first conductor layer 1a with a capacitor insulating film 1c interposed therebetween. One of the first and second conductor layers of the bypass capacitor is connected to one of a grounding wiring line or a power supply wiring lines through a substrate contact which fixes a potential of a substrate and the other is connected to the other of the power supply wiring line or the grounding wiring line.
摘要翻译：提供能够有效地吸收电源噪声的半导体集成电路器件，实现电路的稳定操作，特别是在噪声产生源附近吸收噪声。半导体集成电路器件具有至少一个电路块。半导体集成电路器件包括：旁路电容器，其具有形成在电路块上的第一导体层1a和形成在第一导体层1a上的第二导体层1b，其间插入电容器绝缘膜1c。旁路电容器的第一和第二导体层之一通过固定基板的电位的基板触点而连接到接地布线或电源布线中的一个，另一个连接到电源的另一个接线或接地线。

4. 发明申请

US20050204327A1 Layout data verification method, mask pattern verification method and circuit operation verification method 审中-公开
标题翻译：布局数据验证方法，掩模图案验证方法和电路操作验证方法
公开(公告)号：US20050204327A1
公开(公告)日：2005-09-15
申请号：US11076939
申请日：2005-03-11
申请人： Kiyohito Mukai , Mitsumi Itou , Ritsuko Ozoe , Tatsuo Ohashi , Hiroyuki Tsujikawa
发明人： Kiyohito Mukai , Mitsumi Itou , Ritsuko Ozoe , Tatsuo Ohashi , Hiroyuki Tsujikawa
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , H01L21/82
CPC分类号： G03F1/70 , G03F7/705
摘要： In the verification method of the present invention, a defect that is to cause a problem in fabrication is extracted from a mask pattern. The mask pattern is one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern. The verification method includes the steps of: determining the exposure dose in the photolithography process; simulating the photolithography process on a computer based on the determined exposure dose; checking whether or not the desired design pattern has been obtained; and locating a fault point and outputting the result.
摘要翻译：在本发明的验证方法中，从掩模图案中提取出导致制造中的问题的缺陷。掩模图案是通过使用于光刻工艺中的光掩模的掩模图案变形而获得的，以便提供接近所需设计图案的转印图像。验证方法包括以下步骤：确定光刻工艺中的曝光剂量; 基于所确定的曝光剂量在计算机上模拟光刻工艺; 检查是否获得了所需的设计图案; 并定位故障点并输出结果。

5. 发明授权

US07171645B2 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device 有权
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置
公开(公告)号：US07171645B2
公开(公告)日：2007-01-30
申请号：US10634988
申请日：2003-08-06
申请人： Mitsumi Ito , Junichi Shimada , Kiyohito Mukai , Hiroyuki Tsujikawa
发明人： Mitsumi Ito , Junichi Shimada , Kiyohito Mukai , Hiroyuki Tsujikawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high.A method of generating a pattern for a semiconductor device comprises: a step of designing and arranging a layout pattern of a semiconductor chip; a step of extracting an area ratio of the mask pattern from the layout pattern; and a step of adding and arranging a dummy pattern to the layout pattern, while consideration is given to the most appropriate area ratio of the layout pattern of the layer obtained according to a process condition of the layer composing the layout pattern, so that the area ratio of the layer can be the most appropriate area ratio.
摘要翻译：为了提供能够形成高可靠性的半导体器件的半导体器件的图案生成方法，其精度高。一种生成用于半导体器件的图案的方法包括：设计和布置半导体芯片的布局图案的步骤; 从布局图案提取掩模图案的面积比的步骤; 以及向布局图案添加和布置虚拟图案的步骤，同时考虑根据构成布局图案的层的处理条件获得的层的布局图案的最合适面积比，使得区域该层的比例可以是最合适的面积比。

6. 发明授权

US07062732B2 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device 失效
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及用于半导体装置的图案的制造装置
公开(公告)号：US07062732B2
公开(公告)日：2006-06-13
申请号：US10634989
申请日：2003-08-06
申请人： Mitsumi Ito , Junichi Shimada , Kiyohito Mukai , Hiroyuki Tsujikawa
发明人： Mitsumi Ito , Junichi Shimada , Kiyohito Mukai , Hiroyuki Tsujikawa
IPC分类号： G06F9/45
CPC分类号： H01L23/585 , G06F17/5068 , H01L27/0203 , H01L2924/0002 , Y02T10/82 , H01L2924/00
摘要： To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation of a circuit can be realized.Irrespective of whether or not a region is close to a power supply wiring or a ground wiring, MOS is spread all over a spare area of a chip and connected to a power supply wiring and ground wiring by utilizing a wiring layer and diffusion layer.
摘要翻译：提供一种半导体器件，其特征在于：可以增加去耦电容器; 可以有效地吸收从电源产生的噪声; 并且可以实现电路的稳定操作。无论区域是否接近电源布线或接地布线，MOS都通过利用布线层和扩散层而遍布芯片的备用区域并与电源布线和接地布线相连。

7. 发明授权

US06710449B2 Interconnection structure and method for designing the same 有权
标题翻译：互连结构及其设计方法
公开(公告)号：US06710449B2
公开(公告)日：2004-03-23
申请号：US10101267
申请日：2002-03-20
申请人： Chihiro Hyoto , Kiyoshi Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
发明人： Chihiro Hyoto , Kiyoshi Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
IPC分类号： H01L2348
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-figure pattern made of simple figures is formed and a dummy pattern is formed using the simple-figure pattern. A gap that is not wider than a predetermined value is located in a final wiring pattern made of the wiring pattern and the dummy pattern is defined as an air gap region. Thus, an interconnection structure incorporating air gaps between wiring patterns is formed.
摘要翻译：通过相互不同的值扩大布线图案，从而形成两个放大的布线图案。然后，去除两个放大布线图案彼此重叠的区域，从而形成虚拟图案。或者，形成由简单图形构成的简图，并使用简单图案形成虚拟图案。不大于预定值的间隙位于由布线图案制成的最终布线图形中，并且虚设图案被定义为气隙区域。因此，形成了在布线图案之间并入气隙的互连结构。

8. 发明授权

US06943129B2 Interconnection structure and method for designing the same 失效
标题翻译：互连结构及其设计方法
公开(公告)号：US06943129B2
公开(公告)日：2005-09-13
申请号：US10703605
申请日：2003-11-10
申请人： Chihiro Hyoto , Kiyoshi Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
发明人： Chihiro Hyoto , Kiyoshi Mukai , Hidenori Shibata , Hiroyuki Tsujikawa
IPC分类号： G06F17/50 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-figure pattern made of simple figures is formed and a dummy pattern is formed using the simple-figure pattern. A gap that is not wider than a predetermined value is located in a final wiring pattern made of the wiring pattern and the dummy pattern is defined as an air gap region. Thus, an interconnection structure incorporating air gaps between wiring patterns is formed.
摘要翻译：通过相互不同的值扩大布线图案，从而形成两个放大的布线图案。然后，去除两个放大布线图案彼此重叠的区域，从而形成虚拟图案。或者，形成由简单图形构成的简图，并使用简单图案形成虚拟图案。不大于预定值的间隙位于由布线图案制成的最终布线图形中，并且虚设图案被定义为气隙区域。因此，形成了在布线图案之间并入气隙的互连结构。

9. 发明申请

US20070187777A1 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device 有权
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置
公开(公告)号：US20070187777A1
公开(公告)日：2007-08-16
申请号：US11783465
申请日：2007-04-10
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： H01L29/76 , G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

10. 发明授权

US06490709B1 Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized region 失效
标题翻译：能够改变超大尺寸区域的锁存验证方法和闩锁验证装置
公开(公告)号：US06490709B1
公开(公告)日：2002-12-03
申请号：US09542576
申请日：2000-04-04
申请人： Shinichi Kimura , Hiroyuki Tsujikawa
发明人： Shinichi Kimura , Hiroyuki Tsujikawa
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G06F17/5036
摘要： With respect to layout data of a semiconductor integrated circuit, a latch-up verifying operation is carried out in high precision. In a latch-up verifying method, a well region, a transistor region, and a substrate contact region are extracted from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and steps for separately setting over-sizing values are sequentially executed based upon the respective extracted information.
摘要翻译：对于半导体集成电路的布局数据，以高精度执行闩锁验证操作。在闩锁验证方法中，从形成在半导体衬底上的半导体集成电路的布局数据中提取阱区域，晶体管区域和衬底接触区域; 并且基于相应提取的信息顺序地执行用于单独设置过大尺寸值的步骤。

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