专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06542411B2 Nonvolatile memory and semiconductor device with controlled voltage booster circuit 有权
标题翻译：具有受控升压电路的非易失性存储器和半导体器件
公开(公告)号：US06542411B2
公开(公告)日：2003-04-01
申请号：US09970675
申请日：2001-10-05
申请人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Yoshiki Kawajiri , Masamichi Fujito
发明人： Hiroyuki Tanikawa , Toshihiro Tanaka , Yutaka Shinagawa , Yoshiki Kawajiri , Masamichi Fujito
IPC分类号： G11C1604
CPC分类号： G11C16/3472 , G11C16/30 , G11C16/3468 , G11C16/3481
摘要： A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.
摘要翻译：非易失性存储器包括用于提供关于基本操作（诸如写入，擦除，读取等）的指令的控制寄存器（CRG），用于检测由升压电路升压的电压是否达到期望水平的升压电压达到检测电路，计算施加写入和擦除电压中的每一个所需的时间的电路，以及检测写入或擦除完成的电路。通过将操作指令简单设置到控制寄存器，可以自动提高各自的操作。操作完成后，设置控制寄存器内提供的结束标志（FLAG），通知写入或擦除完成。

2. 发明授权

US06567313B2 Nonvolatile memory, semiconductor device and method of programming to nonvolatile memory 有权
公开(公告)号：US06567313B2
公开(公告)日：2003-05-20
申请号：US09964394
申请日：2001-09-28
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C700
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

3. 发明授权

US06963507B2 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory 有权
公开(公告)号：US06963507B2
公开(公告)日：2005-11-08
申请号：US10419228
申请日：2003-04-21
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C16/02 , G11C8/02 , G11C16/12 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

4. 发明授权

US07376015B2 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory 失效
标题翻译：非易失性存储器，半导体器件和编程到非易失性存储器的方法
公开(公告)号：US07376015B2
公开(公告)日：2008-05-20
申请号：US11197588
申请日：2005-08-05
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C16/06
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.
摘要翻译：公开了一种具有缩短的总写入时间的非易失性存储器，能够通过使写入电流恒定而稳定地写入数据，同时减少由升压电路产生的电压的波动。在诸如闪速存储器的非易失性存储器中，在写入操作时确定数据。在跳过对应于具有逻辑“1”（或逻辑“0”）的写入数据的位时，对与具有逻辑“0”（或逻辑“1”的写入数据相对应的位进行写操作）。

5. 发明申请

US20050265114A1 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory 失效
标题翻译：非易失性存储器，半导体器件和编程到非易失性存储器的方法
公开(公告)号：US20050265114A1
公开(公告)日：2005-12-01
申请号：US11197588
申请日：2005-08-05
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C16/02 , G11C8/02 , G11C16/12
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.
摘要翻译：公开了一种具有缩短的总写入时间的非易失性存储器，能够通过使写入电流恒定而稳定地写入数据，同时减少由升压电路产生的电压的波动。在诸如闪速存储器的非易失性存储器中，在写入操作时确定数据。在跳过对应于具有逻辑“1”（或逻辑“0”）的写入数据的位时，对与具有逻辑“0”（或逻辑“1”的写入数据相对应的位进行写操作）。

6. 发明授权

US07254084B2 Data processing device 有权
公开(公告)号：US07254084B2
公开(公告)日：2007-08-07
申请号：US11138344
申请日：2005-05-27
申请人： Masaaki Terasawa , Yoshiki Kawajiri , Takanori Yamazoe
发明人： Masaaki Terasawa , Yoshiki Kawajiri , Takanori Yamazoe
IPC分类号： G11C5/14 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/32
摘要： A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

7. 发明授权

US07043466B2 Neural network processing system using semiconductor memories 失效
标题翻译：使用半导体存储器的神经网络处理系统
公开(公告)号：US07043466B2
公开(公告)日：2006-05-09
申请号：US09739758
申请日：2000-12-20
申请人： Takao Watanabe , Katsutaka Kimura , Kiyoo Itoh , Yoshiki Kawajiri
发明人： Takao Watanabe , Katsutaka Kimura , Kiyoo Itoh , Yoshiki Kawajiri
IPC分类号： G06N3/06 , G06N3/063 , G06N3/067 , G06N1/00 , G06F15/18
CPC分类号： G06N3/063
摘要： The neural network processing system according to the present invention includes a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit.
摘要翻译：根据本发明的神经网络处理系统包括存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。

8. 发明授权

US06667928B2 Semiconductor device in which a chip is supplied either a first voltage or a second voltage 失效
标题翻译：其中提供芯片的第一电压或第二电压的半导体器件
公开(公告)号：US06667928B2
公开(公告)日：2003-12-23
申请号：US10132248
申请日：2002-04-26
申请人： Kazuki Honma , Yoshiki Kawajiri , Masashi Wada , Mikio Sugawara , Hirofumi Sonoyama
发明人： Kazuki Honma , Yoshiki Kawajiri , Masashi Wada , Mikio Sugawara , Hirofumi Sonoyama
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C5/14 , G11C16/04 , G11C16/30 , G11C29/006 , G11C29/02 , G11C29/12005 , G11C2029/5004
摘要： Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management. The semiconductor chip includes a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.
摘要翻译：公开了一种独特增值的半导体芯片，提高产品的生产率和产量并促进生产管理的半导体集成电路器件，以及制造半导体集成电路器件的方法，其能够提高生产率和产量产品和理性需求响应生产管理。半导体芯片包括在第一电压和第二电压下操作的公共电路块，第二电压高于第一电压，被设计为适合第一电压并与公共电路块一致操作的第一电路块，第二电路块，其被设计成适合第二电压并且与公共电路块一致地操作;以及电压类型建立电路，其激活第一和第二电路块中的一个，电压类型建立电路具有第一识别记录，其指示第一电压块的可操作性电压或第二识别记录，仅指示在芯片所保持的第二电压下的可操作性。

9. 发明授权

US5875347A Neural network processing system using semiconductor memories 失效
标题翻译：使用半导体存储器的神经网络处理系统
公开(公告)号：US5875347A
公开(公告)日：1999-02-23
申请号：US723012
申请日：1996-09-30
申请人： Takao Watanabe , Katsutaka Kimura , Kiyoo Itoh , Yoshiki Kawajiri
发明人： Takao Watanabe , Katsutaka Kimura , Kiyoo Itoh , Yoshiki Kawajiri
IPC分类号： G06F15/18 , G06F17/16 , G06N3/04 , G06N3/063 , G06N99/00 , G06F15/00
CPC分类号： G06N3/063
摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a largescale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.
摘要翻译：这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分在平行下。此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

10. 发明授权

US5822267A Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
公开(公告)号：US5822267A
公开(公告)日：1998-10-13
申请号：US305528
申请日：1994-09-13
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/413 , G11C5/14 , G11C5/147 , G11C8/10 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K5/08 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式