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    • 3. 发明授权
    • Outboard motor
    • 舷外马达
    • US06358108B2
    • 2002-03-19
    • US09767508
    • 2001-01-23
    • Hiroyuki MurataHiroyuki Yoshida
    • Hiroyuki MurataHiroyuki Yoshida
    • B63H2110
    • F02B75/20F02B61/045F02B2075/027F02B2075/1808
    • An outboard motor includes a first case and a second case disposed below the first case. The first case houses therein an oil pan and an upper part of a drive shaft. Within the oil pan, engine oil is held. The second case has its upper edge portion coupled to a lower edge portion of the first case. The second case has a vertical wall disposed therewithin. The vertical wall separates a space within the second case into a cavity and part of an exhaust passage through which exhaust gas passes. The cavity is formed below the oil pan. This arrangement prevents the oil pan from being affected by heat of the exhaust gas. Thus, it becomes possible to prevent the engine oil held within the oil from increasing in temperature.
    • 舷外马达包括第一壳体和设置在第一壳体下方的第二壳体。 第一箱容纳油盘和驱动轴的上部。 在油盘内,保持发动机机油。 第二壳体的上边缘部分联接到第一壳体的下边缘部分。 第二种情况具有设置在其中的垂直壁。 垂直壁将第二壳体内的空间分成空气和废气通过的排气通道的一部分。 空腔形成在油底壳下面。 这种布置防止油底壳受到废气的热的影响。 因此,可以防止保持在油中的发动机油温度升高。
    • 4. 发明授权
    • Resistor unit for a fan speed controller of an automotive air conditioning device
    • 汽车空调设备风扇转速控制器的电阻单元
    • US06173487B1
    • 2001-01-16
    • US09182512
    • 1998-10-30
    • Hiroyuki MurataTakashi IshiiShuko Yamamoto
    • Hiroyuki MurataTakashi IshiiShuko Yamamoto
    • H01C1728
    • H01C1/024H01C1/14Y10T29/49002Y10T29/49082Y10T29/49087Y10T29/49098
    • A fan speed controller of an automotive vehicle air conditioning device is usually placed in an air flow duct to be effectively cooled. Thus, compact construction of the speed controller is needed to obtain a larger air flow in the air flow duct. For this purpose, various compact resistor units for the speed controller have been proposed. However, some of them are poor in durability against shocks. In view of this, a compact resistor unit for a speed controller includes a resistor block that has a flat resistor, a flat insulating plate and a flat radiation plate which are respectively positioned against one another. The compact resistor unit further includes a holder block of molded plastic on which the resistor block is mounted. The compact resistor unit also includes a plurality of metal terminals partially embedded in the holder block, where the terminals are connected to particular portions of the flat resistor. The compact resistor still further includes metal connecting lugs that are partially embedded in the holder block, and rivets for securing the resistor block to the connecting lugs.
    • 机动车空调装置的风扇转速控制器通常放置在空气流动管道中以被有效地冷却。 因此,需要紧凑的速度控制器的结构以获得空气流动管道中的较大的气流。 为此,已经提出了用于速度控制器的各种紧凑型电阻器单元。 然而,其中一些对抗冲击的耐久性较差。 鉴于此,用于速度控制器的紧凑型电阻器单元包括具有平坦电阻器,平坦绝缘板和平坦辐射板的电阻器块,它们分别彼此相对定位。 紧凑型电阻器单元还包括其上安装有电阻器块的模制塑料的保持器块。 紧凑型电阻器单元还包括部分地嵌入保持器块中的多个金属端子,其中端子连接到扁平电阻器的特定部分。 紧凑型电阻器还包括部分地嵌入保持器块中的金属连接凸耳和用于将电阻器块固定到连接凸耳的铆钉。
    • 5. 发明授权
    • Lookup table device and signal conversion method
    • 查找表设备和信号转换方法
    • US5909185A
    • 1999-06-01
    • US945145
    • 1997-10-20
    • Hiroyuki MurataTakashi YokotaKatsuhiro Miura
    • Hiroyuki MurataTakashi YokotaKatsuhiro Miura
    • G06F5/00H03M7/30H03M7/00
    • H03M7/30
    • A lookup table device is provided which converts a digital input signal into a digital output signal previously defined with respect to the digital input signal. The lookup table device has a delimiter information storage unit 10 for storing delimiter information representing a delimiter in a section of the digital input signal corresponding to the digital output signal, a section deriving unit 12 for deriving a section to which a digital input signal belongs, based on the delimiter information stored in the delimiter information storage unit, when the digital input signal is inputted into the lookup table device, and a signal output unit 14 for outputting a digital output signal corresponding to the section derived by the section deriving unit.
    • PCT No.PCT / JP97 / 00443 Sec。 371日期:1997年10月20日 102(e)1997年10月20日的PCT 1997年2月19日提交PCT提供了一种查找表装置,其将数字输入信号转换为相对于数字输入信号预先定义的数字输出信号。 查找表装置具有定界符信息存储单元10,用于存储表示与数字输出信号相对应的数字输入信号的一部分中的定界符的定界符信息;导出数字输入信号所属区段的区间导出单元12; 基于存储在定界符信息存储单元中的定界符信息,当数字输入信号被输入查找表装置时,以及信号输出单元14,用于输出与由区间导出单元导出的区间对应的数字输出信号。
    • 6. 发明申请
    • Information processing unit
    • 信息处理单元
    • US20050169304A1
    • 2005-08-04
    • US11044606
    • 2005-01-28
    • Hiroyuki Murata
    • Hiroyuki Murata
    • G06F13/42G06F13/40H04J3/06H04L7/02H04J3/16
    • G06F13/4059H04J3/0638H04L7/02
    • The object of the invention is to enhance data transmission efficiency by considering a dock frequency, a data transmission method and a data storage method. To achieve the object, an information processing unit according to the invention is provided with a bus on which a data transmission signal is transmitted from the side of a master (a transmission source) to the side of a slave (a transmission destination), another bus on which a data transmission completion signal is transmitted from the slave's side to the masters side, the other bus on which a data signal is transmitted from the master's side to the slave's side, a functional block for converting a protocol on the master's side to a protocol on the slave's side, another functional block for converting the protocol on the slave's side to the protocol on the master's side, registers controlled by a clock on the master's side, registers controlled by a clock on the slave's side, buses for converting from the clock on the masters side to the clock on the slave's side and a bus for converting from the clock on the slave's side to the clock on the master's side.
    • 本发明的目的是通过考虑坞站频率,数据传输方法和数据存储方法来提高数据传输效率。 为了实现该目的,根据本发明的信息处理单元设置有从主机(发送源)侧向从机(发送目的地)一侧发送数据发送信号的总线,另一个 总线,其中数据传输完成信号从从机侧发送到主机侧,另一总线上的数据信号从主机侧发送到从机侧;功能块,用于将主机侧的协议转换为 从机侧的协议,用于将从机侧的协议转换为主机侧的协议的另一个功能块,由主机侧的时钟控制的寄存器,从机侧的时钟控制的寄存器,用于从 主机侧的时钟到从机时钟的时钟和从主机侧的时钟转换到主机侧的时钟的总线。
    • 7. 发明授权
    • Image synthesizing system having a field buffer unit that stores texture
coordinates
    • 具有存储纹理坐标的场缓冲单元的图像合成系统
    • US5553208A
    • 1996-09-03
    • US211395
    • 1994-04-01
    • Hiroyuki MurataTakashi Yokota
    • Hiroyuki MurataTakashi Yokota
    • G06T15/04G09B9/08
    • G06T15/04
    • An image synthesizing system is provided which can increase the speed of its hardware and reduce the scale of the same by using the subsampling/interpolation. A processor unit (80) determines coordinates of each dot and associated texture coordinates in polygons based on image data of vertices. A field buffer unit (40) stores the texture coordinates at its address specified by the coordinates of each dot. The texture coordinates are read out from the field buffer unit (40) and then used to read out rendering data from a texture data storage unit (42) to synthesize and output a pseudo 3-D image. In this case, the processor unit (30) includes a subsampling unit. Texture coordinates of the dots ignored by the subsampling unit are determined on the texture coordinates of dots adjacent to the ignored dots through interpolation circuits (180)-(186).
    • PCT No.PCT / JP93 / 01206 Sec。 371日期1994年04月1日 102(e)1994年4月1日PCT PCT 1993年8月26日PCT公布。 公开号WO94 / 04990 日期1994年3月3日提供一种图像合成系统,可以通过使用子采样/插值来提高其硬件速度并减小其尺寸。 处理器单元(80)基于顶点的图像数据来确定多边形中每个点的坐标和相关联的纹理坐标。 场缓冲器单元(40)将纹理坐标存储在由每个点的坐标指定的地址处。 从场缓冲器单元(40)读出纹理坐标,然后用于从纹理数据存储单元(42)读出绘制数据,以合成并输出伪3-D图像。 在这种情况下,处理器单元(30)包括子采样单元。 通过插值电路(180) - (186),通过子采样单元忽略的点的纹理坐标在与忽略点相邻的点的纹理坐标上确定。
    • 10. 发明授权
    • Information processing apparatus
    • 信息处理装置
    • US07730247B2
    • 2010-06-01
    • US12101474
    • 2008-04-11
    • Hiroyuki Murata
    • Hiroyuki Murata
    • G06F13/14
    • G06F13/364
    • A bus of a SoC (system on chip) includes a system arbiter for controlling not only a command arbiter but also a read information arbiter, a write data control circuit, a write complete notice arbiter and the like. A sequential table containing a series of system operations including activation processing and application processing and an operation clock information circuit or the like that becomes effective when a SoC bus region is divided by an operation clock frequency are utilized in assignment of priority of buses of the system arbiter. Thus, the information transfer efficiency of the whole system bus and the information transfer efficiency of every transfer originator can be improved.
    • SoC(片上系统)的总线包括一个系统仲裁器,用于不仅可以控制一个命令仲裁器,还可以控制一个读取信息仲裁器,一个写入数据控制电路,一个写入完成通知仲裁器等。 包含一系列系统操作的顺序表,包括激活处理和应用处理以及在SoC总线区域被操作时钟频率除以时变得有效的操作时钟信息电路等,被用于系统总线的优先级 仲裁者。 因此,可以提高整个系统总线的信息传输效率和每个传输发起者的信息传输效率。