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1. 发明授权

US09171886B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09171886B2
公开(公告)日：2015-10-27
申请号：US13032359
申请日：2011-02-22
申请人： Hiroyuki Kanaya , Yukinori Koyama , Susumu Shuto , Kuniaki Sugiura
发明人： Hiroyuki Kanaya , Yukinori Koyama , Susumu Shuto , Kuniaki Sugiura
IPC分类号： H01L29/82 , H01L27/22 , H01L21/768 , H01L43/12
CPC分类号： H01L27/228 , H01L21/76897 , H01L43/12
摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.
摘要翻译：根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。存储元件设置在接触插头的上表面上并存储数据。在存储元件上提供布线。

2. 发明申请

US20110266600A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110266600A1
公开(公告)日：2011-11-03
申请号：US13032359
申请日：2011-02-22
申请人： Hiroyuki Kanaya , Yukinori Koyama , Susumu Shuto , Kuniaki Sugiura
发明人： Hiroyuki Kanaya , Yukinori Koyama , Susumu Shuto , Kuniaki Sugiura
IPC分类号： H01L29/82 , H01L21/8246
CPC分类号： H01L27/228 , H01L21/76897 , H01L43/12
摘要： A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element.
摘要翻译：根据实施例的半导体存储器件包括半导体衬底和设置在半导体衬底上的多个开关晶体管。在半导体存储器件中，接触插头嵌入相邻的两个开关晶体管之间，并且与相邻的两个开关晶体管的栅极绝缘。接触插塞也电连接到相邻的两个开关晶体管中的每一个的源极或漏极，并且接触插塞的上表面位于高于开关晶体管的上表面的位置。存储元件设置在接触插头的上表面上并存储数据。在存储元件上设置接线。

3. 发明授权

US5990507A Semiconductor device having ferroelectric capacitor structures 失效
标题翻译：具有铁电电容器结构的半导体器件
公开(公告)号：US5990507A
公开(公告)日：1999-11-23
申请号：US889470
申请日：1997-07-08
申请人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
发明人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11507 , H01L21/76895 , H01L27/10852 , H01L27/11502 , H01L28/55
摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线电容器接触插头。

4. 发明授权

US06190957B1 Method of forming a ferroelectric device 失效
标题翻译：形成铁电体器件的方法
公开(公告)号：US06190957B1
公开(公告)日：2001-02-20
申请号：US09324501
申请日：1999-06-02
申请人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
发明人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
IPC分类号： H01L218242
CPC分类号： H01L27/11507 , H01L21/76895 , H01L27/10852 , H01L27/11502 , H01L28/55
摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线电容器接触插头。

5. 发明授权

US08861251B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08861251B2
公开(公告)日：2014-10-14
申请号：US13423936
申请日：2012-03-19
申请人： Susumu Shuto
发明人： Susumu Shuto
IPC分类号： G11C11/06 , G11C11/16 , H01L27/22
CPC分类号： G11C11/161 , G11C11/06035 , G11C11/16 , G11C11/1659 , G11C11/1673 , H01L27/228
摘要： A semiconductor storage device includes a semiconductor substrate and an active area on the semiconductor substrate. A plurality of cell transistors are formed on the active area. A first bit line and a second bit line are paired with each other. A plurality of word lines intersect the first and second bit lines. A plurality of storage elements respectively has a first end electrically connected to a source or a drain of one of the cell transistors and a second end connected to the first or second bit line. Both of the first and second bit lines are connected to the same active area via the storage elements.
摘要翻译：半导体存储装置包括半导体衬底和半导体衬底上的有源区。在有源区上形成多个单元晶体管。第一位线和第二位线彼此配对。多个字线与第一和第二位线相交。多个存储元件分别具有电连接到单元晶体管之一的源极或漏极的第一端和连接到第一或第二位线的第二端。第一位线和第二位线都通过存储元件连接到相同的有效区域。

6. 发明授权

US07663905B2 Ferroelectric memory device and data read method in same 失效
标题翻译：铁电存储器件和数据读取方法相同
公开(公告)号：US07663905B2
公开(公告)日：2010-02-16
申请号：US11511212
申请日：2006-08-29
申请人： Susumu Shuto
发明人： Susumu Shuto
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C7/04 , G11C7/22
摘要： A ferroelectric memory device includes a memory cell, read circuit, temperature sensing circuit, and read controller. The memory cell includes a ferroelectric capacitor. The read circuit is configured to read data from the memory cell. The temperature sensing circuit is configured to sense the ambient temperature of the memory cell. The read controller is configured to receive a temperature sensing signal from the temperature sensing circuit, and inhibit a data read operation by the read circuit when the temperature sensed by the temperature sensing circuit is higher than a preset temperature.
摘要翻译：铁电存储器件包括存储单元，读电路，温度检测电路和读控制器。存储单元包括铁电电容器。读取电路被配置为从存储器单元读取数据。温度感测电路被配置为感测存储器单元的环境温度。读取控制器被配置为从温度感测电路接收温度感测信号，并且当温度感测电路感测的温度高于预设温度时，禁止读取电路的数据读取操作。

7. 发明授权

US5946231A Non-volatile semiconductor memory device 失效
公开(公告)号：US5946231A
公开(公告)日：1999-08-31
申请号：US72664
申请日：1998-05-05
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

8. 发明申请

US20120314494A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20120314494A1
公开(公告)日：2012-12-13
申请号：US13424163
申请日：2012-03-19
申请人： Susumu Shuto
发明人： Susumu Shuto
IPC分类号： G11C11/14
CPC分类号： H01L27/228 , G11C11/1655 , G11C11/1659
摘要： In a memory, the MTJ elements respectively have a first end electrically connected to any one of a source and a drain of one of the cell transistors. First bit lines each of which is electrically connected to the other one of the source and the drain of one of the cell transistors. Second bit lines each of which is electrically connected to a second end of one of the MTJ elements. Word lines each of which is electrically connected to a gate of one of the cell transistors or functions as a gate of one of the cell transistors. A plurality of the second bit lines correspond to one of the first bit lines. A plurality of the MTJ elements share the same word line and the same active area. The active area is continuously formed in an extending direction of the first and second bit lines.
摘要翻译：在存储器中，MTJ元件分别具有电连接到单元晶体管之一的源极和漏极中的任何一个的第一端。第一位线，其每一个电连接到一个单元晶体管的源极和漏极中的另一个。第二位线各自电连接到一个MTJ元件的第二端。字线，其每一个电连接到一个单元晶体管的栅极，或者用作单元晶体管之一的栅极。多个第二位线对应于第一位线之一。多个MTJ元件共享相同的字线和相同的有效区域。有源区域在第一和第二位线的延伸方向上连续地形成。

9. 发明申请

US20120243303A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120243303A1
公开(公告)日：2012-09-27
申请号：US13231799
申请日：2011-09-13
申请人： Susumu Shuto
发明人： Susumu Shuto
IPC分类号： G11C11/02
CPC分类号： G11C11/00 , G11C11/1659 , G11C11/1673 , G11C11/1675 , Y10S977/935
摘要： A semiconductor storage device according to the present embodiment includes a magnetic tunnel junction element capable of storing data according to a change in resistance state and rewriting the data using a current. A cell transistor is provided for the magnetic tunnel junction element and is placed in a conducting state when a current is allowed to flow through the magnetic tunnel junction element. A current limiter limits a current flowing through the cell transistor and the magnetic tunnel junction element upon data writing.
摘要翻译：根据本实施例的半导体存储装置包括能够根据电阻状态的变化存储数据并使用电流重写数据的磁性隧道结元件。为磁性隧道结元件提供单元晶体管，并且当允许电流流过磁性隧道结元件时将其放置在导通状态。数据写入时，限流器限制流过单元晶体管和磁性隧道结元件的电流。

10. 发明申请

US20120153414A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120153414A1
公开(公告)日：2012-06-21
申请号：US13230755
申请日：2011-09-12
申请人： Susumu Shuto
发明人： Susumu Shuto
IPC分类号： H01L27/10
CPC分类号： H01L27/228
摘要： A semiconductor memory device according to an embodiment includes: a plurality of magnetic tunnel junction elements arranged on a semiconductor substrate; and a plurality of selection transistors electrically connected to first ends of the plurality of magnetic tunnel junction elements. A plurality of first bit lines are respectively connected to the first ends of the magnetic tunnel junction elements via one or more of the selection transistors. A plurality of upper electrodes are respectively connected to second ends of the plurality of magnetic tunnel junction elements. A plurality of second bit lines are respectively connected to the second ends of the magnetic tunnel junction elements via the upper electrodes. The upper electrodes extend along the second bit lines, and one of the upper electrodes is commonly connected to the second ends of the plurality of magnetic tunnel junction elements arranged in an extending direction of the second bit lines.
摘要翻译：根据实施例的半导体存储器件包括：布置在半导体衬底上的多个磁性隧道结元件; 以及电连接到所述多个磁性隧道结元件的第一端的多个选择晶体管。多个第一位线经由一个或多个选择晶体管分别连接到磁性隧道结元件的第一端。多个上电极分别连接到多个磁隧道结元件的第二端。多个第二位线经由上部电极分别连接到磁性隧道结元件的第二端。上电极沿着第二位线延伸，并且上电极中的一个共同地连接到沿第二位线的延伸方向布置的多个磁性隧道结元件的第二端。

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