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1. 发明授权

US06731013B2 Wiring substrate, semiconductor device and package stack semiconductor device 有权
标题翻译：接线基板，半导体器件和封装堆叠半导体器件
公开(公告)号：US06731013B2
公开(公告)日：2004-05-04
申请号：US09873338
申请日：2001-06-05
申请人： Hiroyuki Juso , Yasuki Fukui , Yuji Yano , Seiji Ishihara
发明人： Hiroyuki Juso , Yasuki Fukui , Yuji Yano , Seiji Ishihara
IPC分类号： H01L2348
CPC分类号： H01L24/97 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L25/105 , H01L25/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2224/85001 , H01L2224/97 , H01L2225/06551 , H01L2225/06568 , H01L2225/1011 , H01L2225/1052 , H01L2225/1094 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/30105 , H01L2924/3025 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A wiring substrate of the present invention includes a terminal section, provided on a first surface of an insulating substrate, for wire or flip-chip bondings; a land section, provided on the insulating substrate, for an external connection terminal; wiring patterns, respectively provided on the first surface and a second surface on the other side of the first surface, for making electrical connection between the terminal section and the land section; and a support pattern, provided on the second surface corresponding in position to the terminal section, for improving bondings. The wiring substrate can relieve connection failure in bondings.
摘要翻译：本发明的布线基板包括设置在绝缘基板的第一表面上用于导线或倒装芯片连接的端子部分; 设置在所述绝缘基板上的用于外部连接端子的接地部; 分别设置在第一表面的第一表面和第一表面的另一侧的第二表面上，用于在端子部分和接地部分之间进行电连接; 以及设置在与端子部分相对应的第二表面上的用于改善粘合的支撑图案。接线基板可以缓解接合中的连接故障。

2. 发明申请

US20060278970A1 Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device 有权
标题翻译：半导体器件，堆叠半导体器件以及半导体器件的制造方法
公开(公告)号：US20060278970A1
公开(公告)日：2006-12-14
申请号：US11446189
申请日：2006-06-05
申请人： Yuji Yano , Seiji Ishihara
发明人： Yuji Yano , Seiji Ishihara
IPC分类号： H01L23/12
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49805 , H01L23/49811 , H01L23/49816 , H01L23/5389 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/105 , H01L2224/0554 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48225 , H01L2224/48227 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06558 , H01L2225/06586 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.
摘要翻译：一种半导体器件，包括：基底; 半导体芯片，其形成在所述基底基板上，使得粘合剂层插入在所述半导体芯片和所述基底基板之间; 覆盖半导体芯片的至少一部分的树脂层; 以及外部连接端子，经由布线层与基底基板电连接。外部连接端子与树脂层的表面在同一平面上，并从树脂层露出。利用这种结构，无论半导体器件的连接端子如何，都可以提供在层叠多个半导体器件的情况下具有高连接可靠性的下层半导体器件和堆叠半导体器件堆叠在上层是低的。

3. 发明授权

US07723839B2 Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device 有权
标题翻译：半导体器件，堆叠半导体器件以及半导体器件的制造方法
公开(公告)号：US07723839B2
公开(公告)日：2010-05-25
申请号：US11446189
申请日：2006-06-05
申请人： Yuji Yano , Seiji Ishihara
发明人： Yuji Yano , Seiji Ishihara
IPC分类号： H01L23/12
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49805 , H01L23/49811 , H01L23/49816 , H01L23/5389 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/105 , H01L2224/0554 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48225 , H01L2224/48227 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06558 , H01L2225/06586 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18165 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.
摘要翻译：一种半导体器件，包括：基底; 半导体芯片，其形成在所述基底基板上，使得粘合剂层插入在所述半导体芯片和所述基底基板之间; 覆盖半导体芯片的至少一部分的树脂层; 以及外部连接端子，经由布线层与基底基板电连接。外部连接端子与树脂层的表面在同一平面上，并从树脂层露出。利用这种结构，无论半导体器件的连接端子如何，都可以提供在层叠多个半导体器件的情况下具有高连接可靠性的下级半导体器件和堆叠半导体器件堆叠在上层是低的。

4. 发明授权

US09135966B2 Semiconductor device including memory capable of reducing power consumption 有权
标题翻译：包括能够降低功耗的存储器的半导体装置
公开(公告)号：US09135966B2
公开(公告)日：2015-09-15
申请号：US13566779
申请日：2012-08-03
申请人： Hisashi Iwamoto , Yuji Yano , Kazunari Inoue
发明人： Hisashi Iwamoto , Yuji Yano , Kazunari Inoue
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1096 , G11C7/222
摘要： A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.
摘要翻译：半导体器件包括多个存储器阵列和多个存储器阵列控制电路。多个存储器阵列控制电路中的每一个包括用于控制存储器阵列的读/写操作的读/写控制电路，以及用于基于时钟信号和来自该存储器阵列控制电路的输出信号选择和激活存储器阵列的选择电路读/写控制电路。

5. 发明申请

US20100073533A1 Optical element, optical element wafer, optical element wafer module, optical element module, method for manufacturing optical element module, electronic element wafer module, method for manufacturing electronic element module, electronic element module and electronic information device 有权
标题翻译：光学元件，光学元件晶片，光学元件晶片模块，光学元件模块，光学元件模块的制造方法，电子元件晶片模块，电子元件模块的制造方法，电子元件模块和电子信息装置
公开(公告)号：US20100073533A1
公开(公告)日：2010-03-25
申请号：US12586482
申请日：2009-09-23
申请人： Yuji Yano , Takahiro Nakahashi , Tetsuya Tamiya
发明人： Yuji Yano , Takahiro Nakahashi , Tetsuya Tamiya
IPC分类号： H04N5/335 , G02B7/00 , B32B38/10 , F21V7/00 , B26D7/08
CPC分类号： B29D11/00432 , G02B7/021 , G02B13/0085 , Y10T83/0405 , Y10T156/1075
摘要： An optical element according to the present invention includes: an optical surface at a center portion thereof; a spacer section having a predetermined thickness on an outer circumference side of the optical surface; a support plate including one or a plurality of through holes penetrating the optical surface, inside a transparent resin material; and a penetrating portion and/or a concave portion for releasing the resin material when forming resin, in a further outer peripheral portion of the support plate.
摘要翻译：根据本发明的光学元件包括：在其中心部分处的光学表面; 在所述光学表面的外周侧具有预定厚度的间隔部分; 在透明树脂材料的内部包括贯穿光学面的一个或多个通孔的支撑板; 以及在支撑板的另一外周部分中形成树脂时用于释放树脂材料的穿透部分和/或凹部。

6. 发明申请

US20100073531A1 OPTICAL ELEMENT, OPTICAL ELEMENT WAFER, OPTICAL ELEMENT WAFER MODULE, OPTICAL ELEMENT MODULE, METHOD FOR MANUFACTURING OPTICAL ELEMENT MODULE, ELECTRONIC ELEMENT WAFER MODULE, METHOD FOR MANUFACTURING ELECTRONIC ELEMENT MODULE, ELECTRONIC ELEMENT MODULE AND ELECTRONIC INFORMATION DEVICE 有权
标题翻译：光学元件，光学元件波长，光学元件波长模块，光学元件模块，制造光学元件模块的方法，电子元件波形模块，制造电子元件模块的方法，电子元件模块和电子信息装置
公开(公告)号：US20100073531A1
公开(公告)日：2010-03-25
申请号：US12565444
申请日：2009-09-23
申请人： Yuji Yano , Norimichi Shigemitsu , Kengo Iwai
发明人： Yuji Yano , Norimichi Shigemitsu , Kengo Iwai
IPC分类号： H04N5/335 , G02B7/00 , B32B38/10 , F21V7/00 , B26D3/08
CPC分类号： B26D3/08 , B32B2310/0843 , B32B2457/14 , G02B7/021 , G02B13/003 , H04N5/2254 , H04N5/2257 , Y10T83/0341 , Y10T156/1075
摘要： An optical element according to the present invention includes: an optical surface at a center portion thereof; a spacer section having a predetermined thickness on an outer circumference side of the optical surface; a support plate including one or a plurality of through holes penetrating a portion corresponding to the optical surface, provided inside a transparent resin material, wherein the support plate has light shielding characteristics, an outer circumference portion side of the through hole of the support plate is provided inside the spacer section, and the outer circumference portion side of the through hole is configured to be thicker than a further outer circumference portion side thereof.
摘要翻译：根据本发明的光学元件包括：在其中心部分处的光学表面; 在所述光学表面的外周侧具有预定厚度的间隔部分; 在透明树脂材料的内侧设置有贯通贯穿与光学面对应的部分的一个或多个通孔的支撑板，其中，所述支撑板具有遮光特性，所述支撑板的通孔的外周部侧为设置在所述间隔部的内部，所述贯通孔的外周部侧被配置为比其另外的外周侧更厚。

7. 发明授权

US07683484B2 Bump structure, method of forming bump structure, and semiconductor apparatus using the same 失效
标题翻译：凸起结构，凸块结构的形成方法以及使用其的半导体装置
公开(公告)号：US07683484B2
公开(公告)日：2010-03-23
申请号：US11790143
申请日：2007-04-24
申请人： Yuji Yano , Kazuo Tamaki
发明人： Yuji Yano , Kazuo Tamaki
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L24/11 , H01L24/78 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/1134 , H01L2224/13012 , H01L2224/13016 , H01L2224/13017 , H01L2224/13099 , H01L2224/16106 , H01L2224/2919 , H01L2224/4809 , H01L2224/78301 , H01L2224/83851 , H01L2924/0001 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/00012 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A bump structure includes a squashed ball provided on an electrode pad, and a wire provided on the squashed ball. The wire is a wire loop that is loop-shaped and is formed so as to protrude from an end part of the squashed ball. This provides high bonding reliability between a bonding pad and the bump structure.
摘要翻译：凸起结构包括设置在电极垫上的挤压球，以及设置在挤压球上的线。导线是环形的线环，并且形成为从压扁球的端部突出。这在焊盘和凸块结构之间提供了高的焊接可靠性。

8. 发明授权

US07528011B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US07528011B2
公开(公告)日：2009-05-05
申请号：US11802969
申请日：2007-05-29
申请人： Yuji Yano , Atsuya Narai
发明人： Yuji Yano , Atsuya Narai
IPC分类号： H01L21/00
CPC分类号： H01L24/85 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L25/0657 , H01L25/50 , H01L2224/05553 , H01L2224/05644 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48464 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/48499 , H01L2224/48599 , H01L2224/49052 , H01L2224/4911 , H01L2224/4942 , H01L2224/49425 , H01L2224/49429 , H01L2224/4945 , H01L2224/73265 , H01L2224/78301 , H01L2224/85051 , H01L2224/85181 , H01L2224/85186 , H01L2224/85191 , H01L2224/85203 , H01L2224/85951 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01057 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/4554
摘要： In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.

9. 发明授权

US07113416B2 Associative memory apparatus for searching data in which manhattan distance is minimum 有权
标题翻译：用于搜索曼哈顿距离最小的数据的关联存储装置
公开(公告)号：US07113416B2
公开(公告)日：2006-09-26
申请号：US10915430
申请日：2004-08-11
申请人： Tetsushi Koide , Hans Jurgen Mattausch , Yuji Yano
发明人： Tetsushi Koide , Hans Jurgen Mattausch , Yuji Yano
IPC分类号： G11C7/00
CPC分类号： G11C15/00
摘要： In the present invention, focusing on the point that the number of transistors can be reduced to about ⅖ of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit, and all of the outputs of the absolute-value-of-difference calculating circuits for which the number of comparisons thereof are prepared are input to weight comparison circuits, whereby the calculation of the Manhattan distance between the search data and the reference data is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.
摘要翻译：在本发明中，由于由联结存储器的差值绝对值计算电路由加法电路构成，因此重点在于现有技术中晶体管的数目可以减少到约2/5，和位反转电路。差分绝对值计算电路作为单位比较电路而构成全平行型联想存储器，并且其比较数的差分计算电路的绝对值计算电路的所有输出准备的输入到加权比较电路，由此执行搜索数据和参考数据之间的曼哈顿距离的计算。根据该结构，由于可以通过较少数量的晶体管和小面积来实现曼哈顿距离计算电路，所以可以在低功耗和小面积上实现关联存储装置。

10. 发明申请

US20050162878A1 Associative memory apparatus for searching data in which manhattan distance is minimum 有权
标题翻译：用于搜索曼哈顿距离最小的数据的关联存储装置
公开(公告)号：US20050162878A1
公开(公告)日：2005-07-28
申请号：US10915430
申请日：2004-08-11
申请人： Tetsushi Koide , Hans Mattausch , Yuji Yano
发明人： Tetsushi Koide , Hans Mattausch , Yuji Yano
IPC分类号： G11C15/04 , G06T7/00 , G11C15/00 , G06F7/00
CPC分类号： G11C15/00
摘要： In the present invention, focusing on the point that the number of transistors can be reduced to about ⅖ of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit, and all of the outputs of the absolute-value-of-difference calculating circuits for which the number of comparisons thereof are prepared are input to weight comparison circuits, whereby the calculation of the Manhattan distance between the search data and the reference data is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.
摘要翻译：在本发明中，由于由联结存储器的差值绝对值计算电路由加法电路构成，因此重点在于现有技术中晶体管的数目可以减少到约2/5，和位反转电路。差分绝对值计算电路作为单位比较电路而构成全平行型联想存储器，并且其比较数的差分计算电路的绝对值计算电路的所有输出准备的输入到加权比较电路，由此执行搜索数据和参考数据之间的曼哈顿距离的计算。根据该结构，由于可以通过较少数量的晶体管和小面积来实现曼哈顿距离计算电路，所以可以在低功耗和小面积上实现关联存储装置。

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