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1. 发明授权

US5687382A High speed, reduced power memory system implemented according to access frequency 失效
标题翻译：按照访问频率实现高速，低功耗的存储系统
公开(公告)号：US5687382A
公开(公告)日：1997-11-11
申请号：US473761
申请日：1995-06-07
申请人： Hirotsugu Kojima , Katsuro Sasaki
发明人： Hirotsugu Kojima , Katsuro Sasaki
IPC分类号： G06F12/06 , G06F13/42 , G11C11/00 , G06F1/32 , G11C11/40
CPC分类号： G06F1/3275 , G06F12/0223 , G06F13/4239 , G11C11/005 , G06F2212/1028 , G06F2212/205 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system including a first memory area (MEM-A) implemented using memory units including low threshold voltage transistors powered by a low supply voltage source, and a second memory area (MEM-B) implemented using memory units including higher threshold voltage cells powered by a higher supply voltage source. The first memory area, MEM-A, is designated to contain frequently accessed variables, with less frequently accessed variables designated for storage in the second memory area, MEM-B. The most frequently accessed variables stored in MEM-A provide for fast access at a low power per access power dissipation level due to the lower supply voltage and lower threshold voltage design. Alternatively, the less frequently accessed variables stored in MEM-B require a high power per access, but negligible leakage current during static steady state conditions.
摘要翻译：一种存储器系统，包括使用包括由低电源电压源供电的低阈值电压晶体管的存储器单元实现的第一存储区域（MEM-A）以及使用包括更高阈值电压单元电源的存储器单元实现的第二存储区域（MEM-B）由较高的电源电压源。第一存储区MEM-A被指定为包含经常访问的变量，指定用于存储在第二存储区MEM-B中的较少频率访问的变量。存储在MEM-A中的最常访问的变量由于较低的电源电压和较低的阈值电压设计，能够以低功耗每接入功耗水平快速访问。或者，存储在MEM-B中的较不频繁访问的变量需要每次访问的高功率，而在静态稳态条件期间可忽略不计的漏电流。

2. 发明授权

US5700704A Process for fabricating a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5700704A
公开(公告)日：1997-12-23
申请号：US458615
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.
摘要翻译：提供一种用于制造半导体集成电路器件的方法，该半导体集成电路器件包括具有形成在所述第一电极和所述第二电极之间的第一电极，第二电极和电介质膜的电容器元件。特别地，该方法包括用多晶硅膜形成第一电极和第二电极中的至少一个的步骤，该多晶硅膜通过CVD方法沉积在半导体衬底上，并且在所述沉积期间掺杂有杂质以降低电阻的多晶硅膜。通过该方法形成的电容器元件对静态随机存取存储器件的存储单元特别有用。

3. 发明授权

US5652457A Semiconductor integrated circuit device and process for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5652457A
公开(公告)日：1997-07-29
申请号：US351173
申请日：1994-11-30
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L29/76
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。由两个字线限定的区域配置有两个驱动MISFET和源极线。源极线由与字线的导电层相同的导电层形成。互补数据线的各个数据线由与字线和源极线不同的导电层形成。字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线系统：采用双字线系统使用的子字线。

4. 发明授权

US5005068A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5005068A
公开(公告)日：1991-04-02
申请号：US376953
申请日：1989-07-07
申请人： Shuji Ikeda , Katsuro Sasaki , Kouichi Nagasawa , Satoshi Meguro
发明人： Shuji Ikeda , Katsuro Sasaki , Kouichi Nagasawa , Satoshi Meguro
IPC分类号： H01L21/768 , G11C11/41 , H01L21/8244 , H01L23/522 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904 , Y10S257/906
摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.
摘要翻译：一种静态RAM，其具有由构成存储单元的MISFET的扩展栅极电极和由第一字线分开的第二字线构成的第一字线。 RAM具有用于向存储单元提供诸如地电位的固定电位的布线，布线由与用于形成第二字线的层相同的层形成。

5. 发明授权

US5424972A Carry look ahead circuit 失效
标题翻译：携带前瞻电路
公开(公告)号：US5424972A
公开(公告)日：1995-06-13
申请号：US115737
申请日：1993-09-03
申请人： Norio Ohkubo , Makoto Suzuki , Katsuro Sasaki
发明人： Norio Ohkubo , Makoto Suzuki , Katsuro Sasaki
IPC分类号： G06F7/50 , G06F7/508
CPC分类号： G06F7/508
摘要： A carry look ahead circuit includes a first circuit for generating a logical sum of inputs, a second circuit for generating a logical product of the inputs, and a selection circuit for selecting either one of an output of the first circuit and an output of the second circuit in accordance with a carry signal from a lower figure to produce the selected output as a carry signal. Consequently, the number of circuit elements can be reduced greatly to configure the high speed and low power consumption carry look ahead circuit.
摘要翻译：携带查看电路包括用于产生输入的逻辑和的第一电路，用于产生输入的逻辑积的第二电路和用于选择第一电路的输出和第二电路的输出中的任一个的选择电路根据来自下图的进位信号产生所选择的输出作为进位信号。因此，可以大大减少电路元件的数量，以配置高速和低功耗携带前瞻电路。

6. 发明授权

US5239196A SRAM with dual word lines overlapping drive transistor gates 失效
标题翻译：具有双字线的SRAM与驱动晶体管栅极重叠
公开(公告)号：US5239196A
公开(公告)日：1993-08-24
申请号：US653493
申请日：1991-02-11
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A MOSFET Static Random Access Memory (SRAM) cell has a symmetrical construction, with a pair of word lines. The word lines are in second level polysilicon, so that they may overlap the driving transistor gates which are in first level polysilicon.
摘要翻译： MOSFET静态随机存取存储器（SRAM）单元具有对称结构，具有一对字线。字线处于第二级多晶硅中，使得它们可能与第一级多晶硅中的驱动晶体管栅极重叠。

7. 发明授权

US5134581A Highly stable semiconductor memory with a small memory cell area 失效
标题翻译：高度稳定的半导体存储器具有小的存储单元面积
公开(公告)号：US5134581A
公开(公告)日：1992-07-28
申请号：US604469
申请日：1990-10-29
申请人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu
发明人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu
IPC分类号： G11C11/412 , G11C11/419 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , G11C11/419 , H01L27/1108
摘要： In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)
摘要翻译：为了获得具有小单元区域的高度稳定的SRAM单元，单元比率R被设置为R =（WDEFF / LDEFF）/（WTEFF / LTEFF）<3，其中LDEFF和WDEFF表示有效信道长度，并且有效沟道宽度分别为两个驱动MOSFET 3和4，LTEFF和WTEFF分别表示两个传输MOSFET 5和6的有效沟道长度和有效沟道宽度。此外，流入有源负载MOSFET 1和2的最大电流IR被设置为大于当跨栅极施加阈值电压时流入驱动器MOSFET 5的电流IL（1×10 -8 A），并且 MOSFET 5.一对有源负载MOSFET 1和2堆叠在驱动器MOSFET 3和4以及传输MOSFET 5和6上。

8. 发明授权

US4891792A Static type semiconductor memory with multi-stage sense amplifier 失效
标题翻译：具有多级读出放大器的静态型半导体存储器
公开(公告)号：US4891792A
公开(公告)日：1990-01-02
申请号：US215824
申请日：1988-07-06
申请人： Shoji Hanamura , Masaaki Kubotera , Katsuro Sasaki , Takao Oono , Kiyotsugu Ueda
发明人： Shoji Hanamura , Masaaki Kubotera , Katsuro Sasaki , Takao Oono , Kiyotsugu Ueda
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.
摘要翻译：从静态型半导体存储器的存储单元读出的信息在初级读出放大器，后置放大器和主放大器中进行多级感测放大，然后传输到输出缓冲器电路的输入端。由于均衡电路连接到多级读出放大器的各级的互补输入，所以可以高速执行反向信息读取操作。最初，初级读出放大器，后级读出放大器和主放大器被控制为在高放大增益条件下工作，以便执行高速感测放大，此后被控制以在低功耗条件下工作，通过高速感测放大获得的输出信息输出不会消失。

9. 发明授权

US06473333B1 Storage circuit with layered structure element 失效
标题翻译：具有分层结构元件的存储电路
公开(公告)号：US06473333B1
公开(公告)日：2002-10-29
申请号：US09986946
申请日：2001-11-13
申请人： Suguru Tachibana , Katsuro Sasaki , Kiyoo Itoh , Tomoyuki Ishii
发明人： Suguru Tachibana , Katsuro Sasaki , Kiyoo Itoh , Tomoyuki Ishii
IPC分类号： G11C1140
CPC分类号： G11C11/22 , G11C11/412 , G11C14/00 , Y10S257/903
摘要： The present invention provides a circuit, in which a device typified by a PLED element is built into a flip-flop. In this case, a storage node of the device is low leakage. According to the present invention, it is possible to realize a SRAM that has nonvolatility while achieving high-speed operation. It is also possible to realize a flip-flop having the same characteristics. An example of a typical mode of the present invention is a storage circuit characterized by the following: a storage element is a device incorporating: a first path for a carrier; a first mode for storing a charge that generates an electric field where conductivity of the first path is changed; and a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node; and the storage circuit includes a second node, to which information stored in the first node is outputted steadily in a state in which power is supplied. The flip-flop and the SRAM are realized using such a basic circuit.
摘要翻译：本发明提供了一种电路，其中以触发器构建由PLED元件代表的器件。在这种情况下，设备的存储节点是低泄漏。根据本发明，可以实现具有非易失性的SRAM，同时实现高速操作。也可以实现具有相同特性的触发器。本发明的典型模式的一个例子是存储电路，其特征在于：存储元件是包括：用于载体的第一路径的装置; 用于存储产生第一路径的导电性改变的电场的电荷的第一模式; 以及阻挡结构，第二载体通过该阻挡结构响应于给定的电压移动，使得第二载体被存储在第一节点中; 并且存储电路包括第二节点，第一节点中存储的信息在供电的状态下稳定地输出。使用这样的基本电路来实现触发器和SRAM。

10. 发明授权

US5767554A Semiconductor integrated circuit device and process for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5767554A
公开(公告)日：1998-06-16
申请号：US460639
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。由两个字线限定的区域配置有两个驱动MISFET和源极线。源极线由与字线的导电层相同的导电层形成。互补数据线的各个数据线由与字线和源极线不同的导电层形成。字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线系统：采用双字线系统使用的子字线。

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