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1. 发明授权

US06257855B1 Screw fluid machine 有权
标题翻译：螺旋流体机
公开(公告)号：US06257855B1
公开(公告)日：2001-07-10
申请号：US09442467
申请日：1999-11-18
申请人： Hirotaka Kameya , Shigekazu Nozawa , Masayuki Urashin , Takeshi Hida , Masakazu Aoki
发明人： Hirotaka Kameya , Shigekazu Nozawa , Masayuki Urashin , Takeshi Hida , Masakazu Aoki
IPC分类号： F03C200
CPC分类号： F04C18/084 , F04C18/16
摘要： A screw rotor for use in screw compressors and screw vacuum pumps comprises a pair of rotors including a male rotor and a female rotor. These rotors have helical lobes in an axial direction and mesh with each other to form a compression chamber. Depending upon a lobe configuration of the rotors, suction pressure and discharge pressure, a negative torque for self-rotation as well as a positive torque opposing to rotation due to a compression action is generated on the female rotor in operation. This phenomenon generates when a value obtained by integrating a torque acting on the female rotor over an entire cross section in an axial direction of the rotors becomes negative. When the negative torque is generated, noises due to tooth separating vibration is caused. Then, a lobe profile is defined such that a magnitude of the negative torque is smaller than that of the positive torque in respective cross sections of the female rotor. That is, a relationship between a radius of a point of contact on a leading surface side of the female rotor and a radius of a point of contact on a trailing surface side or curvatures of the rotors are such that the negative torque is not generated on the lobe profile.
摘要翻译：用于螺杆式压缩机和螺杆式真空泵的螺杆转子包括一对转子，包括一个公转子和一个母转子。这些转子在轴向上具有螺旋形叶片并且彼此啮合以形成压缩室。根据转子的凸角构造，吸入压力和排出压力，在操作中在母转子上产生自旋转的负转矩以及由于压缩动作而与旋转相反的正转矩。当通过将在母转子上作用的转矩在转子的轴向上的整个横截面上积分得到的值变为负时，会产生这种现象。当产生负转矩时，会引起由于齿分离振动引起的噪音。然后，定义凸角轮廓，使得负转矩的大小小于阴转子的相应横截面中的正转矩的大小。也就是说，阴转子的前表面侧的接触点的半径与后表面侧的接触点的半径或转子的曲率之间的关系使得不产生负转矩肺叶剖面。

2. 发明授权

US08672647B2 Water injected scroll air compressor 有权
标题翻译：注水涡旋空压机
公开(公告)号：US08672647B2
公开(公告)日：2014-03-18
申请号：US13024123
申请日：2011-02-09
申请人： Natsuki Kawabata , Kazuaki Shiinoki , Hirotaka Kameya , Masakazu Aoki
发明人： Natsuki Kawabata , Kazuaki Shiinoki , Hirotaka Kameya , Masakazu Aoki
IPC分类号： F01C1/02
CPC分类号： F04C18/0215 , F04C18/0223 , F04C18/0253 , F04C28/06 , F04C28/08 , F04C28/24 , F04C29/042 , F04C2270/19 , F04C2270/80
摘要： A high reliability water injected scroll air compressor is provided with an orbiting scroll, a fixed scroll corresponding to the orbiting scroll, a motor that generates driving force for making the orbiting scroll orbit the fixed scroll, a compressing path from a suction port to a discharge port, and a portion for injecting water into the compressing path. The operation is controlled by a switching operation in which water is injected into the compressing path and then no water is injected. Corrosion, failure of activation, and concerns about wrap contact when water is injected into an air end are avoided by switching the operation with water injection and the operation without water injection so as to prevent water from remaining in the air end.
摘要翻译：高可靠性注水涡旋式空气压缩机设有绕动涡旋盘，对应于绕动涡盘的固定涡旋盘，产生驱动力的马达，用于使绕动涡盘盘绕固定涡旋盘，从吸入口到排气口的压缩路径端口和用于将水注入压缩路径的部分。通过将水注入到压缩路径中并且没有水被注入的切换操作来控制操作。当水注入空气端时，腐蚀，活化失败以及对水分接触的担忧，避免了注水操作和无需注水的操作，以防止水留在空气端。

3. 发明授权

US07750668B2 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有降压机构的半导体集成电路装置
公开(公告)号：US07750668B2
公开(公告)日：2010-07-06
申请号：US11979100
申请日：2007-10-31
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19/003 , G05F1/10 , G06F1/32
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

4. 发明授权

US07391998B2 Developing apparatus 失效
标题翻译：开发设备
公开(公告)号：US07391998B2
公开(公告)日：2008-06-24
申请号：US11353077
申请日：2006-02-14
申请人： Masakazu Aoki , Akinobu Okuda , Hironobu Kinoshita , Hideki Yasuda , Kazumasa Hayashi
发明人： Masakazu Aoki , Akinobu Okuda , Hironobu Kinoshita , Hideki Yasuda , Kazumasa Hayashi
IPC分类号： G03G15/08
CPC分类号： G03G15/0893 , G03G15/0877 , G03G2215/0833
摘要： The present invention provides a developing apparatus to be provided in a quick start up electrophotographic image forming apparatus that can efficiently prevent generation of unevenness by a screw pitch in a short period of time. The developing apparatus rotates a developer transporting screw so as to transport and supply a developer to a developer bearing member, and develops a latent image formed on an image bearing member by the developer. The developer transporting screw includes a vane winding around a rotation shaft in a spiral form. A vane surface on other side of a developer transport direction of the vane includes two planes having different angles with a rotational center line of the rotation shaft. Relationships of θ2
摘要翻译：本发明提供一种显影装置，其设置在快速启动电子照相图像形成装置中，其能够在短时间内有效地防止螺距的产生。显影装置旋转显影剂输送螺杆，以便将显影剂输送并供应到显影剂承载部件，并且通过显影剂显影形成在图像承载部件上的潜像。显影剂输送螺杆包括以螺旋形式围绕旋转轴缠绕的叶片。在叶片的显影剂输送方向的另一侧的叶片表面包括与旋转轴的旋转中心线具有不同角度的两个平面。满足θ2θ和10°<θ2 <= 60°的关系，其中θ1表示与旋转中心线之间的距离较长的平面之间的角度; 和旋转中心线，θ2表示与旋转中心线具有较短距离的面之间的角度; 和旋转中心线。

5. 发明申请

US20050023615A1 Semiconductor element and semiconductor memory device using the same 失效
标题翻译：半导体元件和使用其的半导体存储器件
公开(公告)号：US20050023615A1
公开(公告)日：2005-02-03
申请号：US10929424
申请日：2004-08-31
申请人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
发明人： Kazuo Yano , Tomoyuki Ishii , Takashi Hashimoto , Koichi Seki , Masakazu Aoki , Takeshi Sakata , Yoshinobu Nakagome , Kan Takeuchi
IPC分类号： H01L21/8247 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/04 , G11C16/28 , H01L21/28 , H01L21/336 , H01L27/01 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/66 , H01L29/76 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/036 , H01L31/062 , H01L31/112 , H01L31/113
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/404 , G11C16/02 , G11C16/0466 , G11C16/10 , G11C16/28 , G11C2216/06 , G11C2216/08 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L27/1203 , H01L29/42328 , H01L29/513 , H01L29/66825 , H01L29/7613 , H01L29/785 , H01L29/7888
摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.
摘要翻译：一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

6. 发明授权

US06611458B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06611458B2
公开(公告)日：2003-08-26
申请号：US09780393
申请日：2001-02-12
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： G11C1606
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.
摘要翻译：为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮置电极的非易失性存储元件，通过第一层多晶硅或非易失性存储元件在对半导体集成电路进行测试时被编程，从而在形成非易失性存储元件时不需要特殊工艺，也就是说，可以在形成CMOS器件和器件的过程中形成非易失性存储元件用于编程的激光束不需要，因为在测试中进行编程，可以缩短编程所需的时间，因此可以降低测试成本。

7. 发明授权

US06175251B1 Semiconductor integrated circuit device having power reduction 有权
标题翻译：具有功率降低的半导体集成电路器件
公开(公告)号：US06175251B1
公开(公告)日：2001-01-16
申请号：US09291957
申请日：1999-04-15
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K190948
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

8. 发明授权

US5926430A Semiconductor integrated circuit device and method of activating the same 失效
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US5926430A
公开(公告)日：1999-07-20
申请号：US985425
申请日：1997-12-05
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , H03K19/00 , H03K17/16
CPC分类号： G11C5/14 , G11C11/4074 , G11C5/147 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线的并行设置多个开关MOSFET，其在达到其非电压时不需要存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

9. 发明授权

US5818792A Semiconductor memory device and memory module using the same 失效
标题翻译：半导体存储器件和使用其的存储器模块
公开(公告)号：US5818792A
公开(公告)日：1998-10-06
申请号：US804683
申请日：1997-02-25
申请人： Toshio Sasaki , Kazumasa Yanagisawa , Toshio Sugano , Kiyoshi Inoue , Seiichiro Tsukui , Masakazu Aoki , Shigeru Suzuki , Masashi Horiguchi
发明人： Toshio Sasaki , Kazumasa Yanagisawa , Toshio Sugano , Kiyoshi Inoue , Seiichiro Tsukui , Masakazu Aoki , Shigeru Suzuki , Masashi Horiguchi
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/108 , G01C13/00
CPC分类号： G11C29/80 , G11C29/74 , G11C29/808 , G11C29/832
摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.
摘要翻译：第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障在记忆垫单位。电源基本上被切断供给故障存储器垫。

10. 发明授权

US5617365A Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US5617365A
公开(公告)日：1997-04-01
申请号：US535574
申请日：1995-09-27
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the memory array is divided into memory mats. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there are provided, address comparing circuits each of which storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address, and selection circuitry including logical OR gates for replacing a defective bit line by a spare bit line in accordance with the result of the comparison. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
摘要翻译：引入冗余技术用于半导体存储器，更具体地，涉及具有16兆位或更多存储容量的动态随机存取存储器（DRAM）的冗余技术。在这样的DRAM中，存储器阵列被分成存储器垫。根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于提供两级交叉口中的期望的和备用位线，提供地址比较电路，每个存储器存储存储器阵列中存在的缺陷地址，并将要访问的地址与存储的缺陷地址进行比较，以及选择电路包括用于根据比较结果用备用位线替换有缺陷位线的逻辑“或”门。每个地址比较电路在其中存储有缺陷位线的列地址和指示与有缺陷位线对应的存储器堆的行地址的一部分。

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