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1. 发明授权

US5652180A Method of manufacturing semiconductor device with contact structure 失效
标题翻译：具有接触结构的半导体器件的制造方法
公开(公告)号：US5652180A
公开(公告)日：1997-07-29
申请号：US264928
申请日：1994-06-24
申请人： Hiroshi Shinriki , Hiroshi Yamamoto , Nobuyuki Takeyasu , Takayuki Komiya , Tomohiro Ohta
发明人： Hiroshi Shinriki , Hiroshi Yamamoto , Nobuyuki Takeyasu , Takayuki Komiya , Tomohiro Ohta
IPC分类号： H01L21/768 , H01L21/285
CPC分类号： H01L21/76879 , H01L2924/0002
摘要： A semiconductor device with a contact structure includes a silicon substrate, a diffusion region formed in a surface of the silicon substrate, a silicide film of high melting point metal deposited on the diffusion region, an insulating film formed on the silicon substrate, a contact hole formed in the insulating film such that the silicide film is exposed at a bottom of the contact hole, an anti-diffusion film formed on the exposed surface of the silicide film at the bottom of the contact film, a plug formed in the contact hole by a selective Al CVD, and a metal wiring formed on the insulating film such that the metal wiring is electrically connected to the diffusion region by means of the plug, anti-diffusion film and silicide film. The anti-diffusion film may be formed by nitriding the surface of the silicide film.
摘要翻译：具有接触结构的半导体器件包括硅衬底，形成在硅衬底的表面中的扩散区，沉积在扩散区上的高熔点金属的硅化物膜，形成在硅衬底上的绝缘膜，接触孔形成在绝缘膜上，使得硅化物膜暴露在接触孔的底部，形成在接触膜底部的硅化物膜的暴露表面上的防扩散膜，通过接触孔形成的插塞选择性Al CVD，以及形成在绝缘膜上的金属布线，使得金属布线通过插塞，防扩散膜和硅化物膜电连接到扩散区。抗扩散膜可以通过氮化硅化物膜的表面而形成。

2. 发明授权

US5627102A Method for making metal interconnection with chlorine plasma etch 失效
标题翻译：用氯等离子体蚀刻制造金属互连的方法
公开(公告)号：US5627102A
公开(公告)日：1997-05-06
申请号：US569319
申请日：1995-12-08
申请人： Hiroshi Shinriki , Takeshi Kaizuka , Nobuyuki Takeyasu , Tomohiro Ohta , Eiichi Kondoh , Hiroshi Yamamoto , Tomoharu Katagiri , Tadashi Nakano , Yumiko Kawano
发明人： Hiroshi Shinriki , Takeshi Kaizuka , Nobuyuki Takeyasu , Tomohiro Ohta , Eiichi Kondoh , Hiroshi Yamamoto , Tomoharu Katagiri , Tadashi Nakano , Yumiko Kawano
IPC分类号： H01L21/285 , H01L21/3213 , H01L21/768 , H01L21/28
CPC分类号： H01L21/76838 , H01L21/28556 , H01L21/32136 , H01L21/76843 , H01L21/76856 , H01L21/76865 , H01L21/76877 , H01L23/53223 , H01L2924/0002
摘要： A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage. The thus fabricated metal interconnection has improved reliability including electromigration immunity when used in semiconductor devices and finding advantageous use in miniaturized semiconductor devices.
摘要翻译：通过在半导体衬底之上形成诸如Ti和/或高熔点金属化合物如TiN层的高熔点金属的下面的金属膜，在等离子体中蚀刻下面的金属膜的表面，在含有并在下面的金属膜上形成诸如Al，Cu，Au和Ag的互连金属膜。或者，通过在半导体衬底上形成绝缘膜，在绝缘膜上形成连接孔，通过CVD在绝缘膜上形成TiN等下面的金属膜，形成连接孔的底壁和侧壁，形成金属互连在控制条件下进行处理，并在底层金属膜上形成互连金属膜如Al。 TiN膜具有（111）优先取向，铝膜具有（111）优先取向，表面光滑，有效覆盖。如此制造的金属互连具有改进的可靠性，包括当用于半导体器件中的电迁移抗扰性并且在小型化的半导体器件中发现有利的用途。

3. 发明授权

US5952723A Semiconductor device having a multilevel interconnection structure 失效
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US5952723A
公开(公告)日：1999-09-14
申请号：US827411
申请日：1997-03-27
申请人： Nobuyuki Takeyasu , Hiroshi Yamamoto , Yumiko Kawano , Eiichi Kondoh , Tomoharu Katagiri , Tomohiro Ohta
发明人： Nobuyuki Takeyasu , Hiroshi Yamamoto , Yumiko Kawano , Eiichi Kondoh , Tomoharu Katagiri , Tomohiro Ohta
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L23/53223 , H01L21/76802 , H01L21/76879 , H01L23/5226 , H01L2924/0002
摘要： A semiconductor device has a multilevel interconnection structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and at least one via hole. The via plug partially fills the via hole, and the upper surface of the via plug may have a convex shape or a surface of the lower wiring layer at a bottom of the via hole may have a concave shape. Where two via holes are present, one via plug substantially fills the shallowest via hole, and partially fills the deepest via hole. The upper wiring layer may be formed over the via plug to fill a remaining portion of the via hole not filled by the via plug.
摘要翻译：半导体器件具有多层互连结构，其包括形成在下布线层，半导体衬底和至少一个通孔上的绝缘夹层。通孔插头部分地填充通孔，并且通孔插塞的上表面可以具有凸形形状，或者在通孔的底部的下布线层的表面可以具有凹形。当存在两个通孔时，一个通孔插塞基本上填满最浅的通孔，并且部分填充最深的通孔。上部布线层可以形成在通孔塞上，以填充未由通孔插塞填充的通孔的剩余部分。

4. 发明授权

US5637534A Method of manufacturing semiconductor device having multilevel interconnection structure 失效
标题翻译：制造具有多层互连结构的半导体器件的方法
公开(公告)号：US5637534A
公开(公告)日：1997-06-10
申请号：US172717
申请日：1993-12-27
申请人： Nobuyuki Takeyasu , Hiroshi Yamamoto , Yumiko Kawano , Eiichi Kondoh , Tomoharu Katagiri , Tomohiro Ohta
发明人： Nobuyuki Takeyasu , Hiroshi Yamamoto , Yumiko Kawano , Eiichi Kondoh , Tomoharu Katagiri , Tomohiro Ohta
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L23/53223 , H01L21/76802 , H01L21/76879 , H01L23/5226 , H01L2924/0002
摘要： A semiconductor device has a multilayered structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and a via hole. The semiconductor device is manufactured by a method that includes plasma etching at least one surface of the insulating interlayer the in an atmosphere having as a major component either a carbonless, chlorine-based gas or a carbonless, chlorine-based gas and an inactive gas in order to remove contaminates that would otherwise promote reactivity with aluminum CVD on the surface of the insulating interlayer.
摘要翻译：半导体器件具有多层结构，其包括形成在下布线层，半导体衬底和通孔上的绝缘中间层。半导体器件通过以下方法制造：包括在作为主要成分的无碳，氯系气体或无碳，氯系气体和惰性气体的气氛中等离子体蚀刻绝缘夹层的至少一个表面以去除否则将促进绝缘中间层表面上的铝CVD的反应性的污染物。

5. 发明授权

US5627345A Multilevel interconnect structure 失效
标题翻译：多层互连结构
公开(公告)号：US5627345A
公开(公告)日：1997-05-06
申请号：US198788
申请日：1994-02-18
申请人： Hiroshi Yamamoto , Tomohiro Ohta , Nobuyuki Takeyasu
发明人： Hiroshi Yamamoto , Tomohiro Ohta , Nobuyuki Takeyasu
IPC分类号： H01L23/522 , H01L23/532 , H05K1/09 , H05K1/14
CPC分类号： H01L21/76852 , H01L21/76885 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , Y10T29/49126 , Y10T29/49165
摘要： A multilevel interconnect structure for use in a semiconductor device includes a lower metal wiring having an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film. An interlayer insulating film is deposited on the lower metal wiring and a via hole is formed in the interlayer insulating film. A plug made of aluminum or aluminum alloy is formed in the via hole. An upper metal wiring has an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film. The plug directly contacts the aluminum or aluminum alloy film of at least one of the lower and upper metal wirings to decrease the via resistance without reducing the electromigration reliability.
摘要翻译：用于半导体器件的多层互连结构包括具有铝或铝合金膜和高熔点金属或高熔点金属合金膜的下金属布线。层间绝缘膜沉积在下金属布线上，并且在层间绝缘膜中形成通孔。在通孔中形成由铝或铝合金制成的塞子。上金属布线具有铝或铝合金膜和高熔点金属或高熔点金属合金膜。插头直接接触下部和上部金属布线中的至少一个的铝或铝合金膜以降低通孔电阻而不降低电迁移可靠性。

6. 发明授权

US5486492A Method of forming multilayered wiring structure in semiconductor device 失效
标题翻译：在半导体器件中形成多层布线结构的方法
公开(公告)号：US5486492A
公开(公告)日：1996-01-23
申请号：US142971
申请日：1993-10-29
申请人： Hiroshi Yamamoto , Nobuyuki Takeyasu , Tomohiro Ohta
发明人： Hiroshi Yamamoto , Nobuyuki Takeyasu , Tomohiro Ohta
IPC分类号： H01L21/768 , H01L21/285 , H01L21/3065
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76862 , H01L21/76879
摘要： A method of forming a via structure having good characteristics in a semiconductor device having a multilayered wiring structure includes forming a thin film including a high melting point metal or a high melting point metal compound on at least the side wall of a via hole before a via plug including Al or an Al alloy is formed.
摘要翻译：在具有多层布线结构的半导体器件中形成具有良好特性的通孔结构的方法包括在通孔之前至少在通孔的侧壁上形成包括高熔点金属或高熔点金属化合物的薄膜形成包括Al或Al合金的塞子。

7. 发明授权

US06063703A Method for making metal interconnection 失效
标题翻译：金属互连方法
公开(公告)号：US06063703A
公开(公告)日：2000-05-16
申请号：US81047
申请日：1998-05-19
申请人： Hiroshi Shinriki , Takeshi Kaizuka , Nobuyuki Takeyasu , Tomohiro Ohta , Eiichi Kondoh , Hiroshi Yamamoto , Tomoharu Katagiri , Tadashi Nakano , Yumiko Kawano
发明人： Hiroshi Shinriki , Takeshi Kaizuka , Nobuyuki Takeyasu , Tomohiro Ohta , Eiichi Kondoh , Hiroshi Yamamoto , Tomoharu Katagiri , Tadashi Nakano , Yumiko Kawano
IPC分类号： H01L21/285 , H01L21/3213 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76838 , H01L21/28556 , H01L21/32136 , H01L21/76843 , H01L21/76856 , H01L21/76865 , H01L21/76877 , H01L23/53223 , H01L2924/0002
摘要： A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connecting holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage. The thus fabricated metal interconnection has improved reliability including electromigration immunity when used in semiconductor devices and finding advantageous use in miniaturized semiconductor devices.
摘要翻译：通过在半导体衬底之上形成诸如Ti和/或高熔点金属化合物如TiN层的高熔点金属的下面的金属膜，在等离子体中蚀刻下面的金属膜的表面，在含有并在下面的金属膜上形成诸如Al，Cu，Au和Ag的互连金属膜。或者，通过在半导体衬底上形成绝缘膜，在绝缘膜上形成连接孔，在绝缘膜上形成诸如TiN的下面的金属膜和连接孔的底壁和侧壁，通过CVD 在控制条件下进行处理，并在底层金属膜上形成互连金属膜如Al。 TiN膜具有（111）优先取向，铝膜具有（111）优先取向，表面光滑，有效覆盖。如此制造的金属互连具有改进的可靠性，包括当用于半导体器件中的电迁移抗扰性并且在小型化的半导体器件中发现有利的用途。

8. 发明授权

US5973402A Metal interconnection and method for making 失效
标题翻译：金属互连和制造方法
公开(公告)号：US5973402A
公开(公告)日：1999-10-26
申请号：US791161
申请日：1997-01-30
申请人： Hiroshi Shinriki , Takeshi Kaizuka , Nobuyuki Takeyasu , Tomohiro Ohta , Eiichi Kondoh , Hiroshi Yamamoto , Tomoharu Katagiri , Tadashi Nakano , Yumiko Kawano
发明人： Hiroshi Shinriki , Takeshi Kaizuka , Nobuyuki Takeyasu , Tomohiro Ohta , Eiichi Kondoh , Hiroshi Yamamoto , Tomoharu Katagiri , Tadashi Nakano , Yumiko Kawano
IPC分类号： H01L21/285 , H01L21/3213 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76838 , H01L21/28556 , H01L21/32136 , H01L21/76843 , H01L21/76856 , H01L21/76865 , H01L21/76877 , H01L23/53223 , H01L2924/0002
摘要： A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage. The thus fabricated metal interconnection has improved reliability including electromigration immunity when used in semiconductor devices and finding advantageous use in miniaturized semiconductor devices.
摘要翻译：通过在半导体衬底之上形成诸如Ti和/或高熔点金属化合物如TiN层的高熔点金属的下面的金属膜，在等离子体中蚀刻下面的金属膜的表面，在含有并在下面的金属膜上形成诸如Al，Cu，Au和Ag的互连金属膜。或者，通过在半导体衬底上形成绝缘膜，在绝缘膜上形成连接孔，通过CVD在绝缘膜上形成TiN等下面的金属膜，形成连接孔的底壁和侧壁，形成金属互连在控制条件下进行处理，并在底层金属膜上形成互连金属膜如Al。 TiN膜具有（111）优先取向，铝膜具有（111）优先取向，表面光滑，有效覆盖。如此制造的金属互连具有改进的可靠性，包括当用于半导体器件中的电迁移抗扰性并且在小型化的半导体器件中发现有利的用途。

9. 发明授权

US5946799A Multilevel interconnect method of manufacturing 失效
标题翻译：多层互连制造方法
公开(公告)号：US5946799A
公开(公告)日：1999-09-07
申请号：US768557
申请日：1996-12-18
申请人： Hiroshi Yamamoto , Tomohiro Ohta , Nobuyuki Takeyasu
发明人： Hiroshi Yamamoto , Tomohiro Ohta , Nobuyuki Takeyasu
IPC分类号： H01L23/522 , H01L23/532 , H01K3/10
CPC分类号： H01L21/76852 , H01L21/76885 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , Y10T29/49126 , Y10T29/49165
摘要： In a multilevel interconnect structure for use in a semiconductor device including a lower metal wiring having an aluminum or aluminum alloy film and a high melting point metal or high melting metal alloy film, an interlayer insulating film deposited on the lower metal wiring, a via hole formed in the interlayer insulating film, a plug made of aluminum or aluminum alloy and formed in the via hole, and an upper metal wiring having an aluminum or aluminum alloy film and a high melting point metal or high melting point metal alloy film, said plug is directly contacted with the aluminum or aluminum alloy film of at least one of the lower and upper metal wirings to decrease the via resistance without reducing the electromigration reliability. The plug is formed such that its top portion protrudes from the interlayer insulating film, the high melting point metal or high melting point metal alloy film of the upper metal wiring is formed, and then the top portion of the plug is removed together with a part of the high melting point metal or high melting point metal alloy film by a chemical mechanical polishing to expose an upper end of the plug. Then, the aluminum or aluminum alloy film of the upper metal wiring is formed to be brought into direct contact with the plug.
摘要翻译：在用于包括具有铝或铝合金膜和高熔点金属或高熔点金属合金膜的下金属布线的半导体器件的多电平互连结构中，沉积在下金属布线上的层间绝缘膜，通孔形成在层间绝缘膜中的铝或铝合金制成的插塞，并形成在通孔中，以及具有铝或铝合金膜和高熔点金属或高熔点金属合金膜的上金属布线，所述插头与下部和上部金属布线中的至少一个的铝或铝合金膜直接接触以降低通孔电阻而不降低电迁移可靠性。插头形成为使其顶部从层间绝缘膜突出，形成上金属布线的高熔点金属或高熔点金属合金膜，然后将塞子的顶部与一部分的高熔点金属或高熔点金属合金膜通过化学机械抛光以暴露插塞的上端。然后，上金属布线的铝或铝合金膜形成为与插头直接接触。

10. 发明授权

US6001736A Method of manufacturing semiconductor device and an apparatus for manufacturing the same 失效
标题翻译：半导体装置的制造方法及其制造装置
公开(公告)号：US6001736A
公开(公告)日：1999-12-14
申请号：US610341
申请日：1996-03-04
申请人： Eiichi Kondo , Nobuyuki Takeyasu , Tomohiro Ohta , Yumiko Kawano , Takeshi Kaizuka , Shinpei Jinnouchi
发明人： Eiichi Kondo , Nobuyuki Takeyasu , Tomohiro Ohta , Yumiko Kawano , Takeshi Kaizuka , Shinpei Jinnouchi
IPC分类号： H01L21/306 , H01L21/768 , H01L21/441
CPC分类号： H01L21/02068 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76877
摘要： An insulating layer is provided on a semiconductor substrate, a contact hole is formed in the insulating layer, and an underlying metal film is provided on a whole surface of the substrate including inner walls of the contact hole. A surface condition of the underlying metal film is adjusted by a hydrogen plasma treatment. By the hydrogen plasma treatment, a surface of the underlying metal film is hydrogenated and is sputter-etched, so that a disordered film and contaminants adsorbed on the surface of the underlying metal film are removed. Next, aluminum is deposited on the underlying metal film by a chemical vapor deposition process using an organic aluminum compound such as DMAH. The contact hole can be effectively filled with aluminum.
摘要翻译：绝缘层设置在半导体衬底上，在绝缘层中形成接触孔，并且在包括接触孔的内壁的衬底的整个表面上设置下面的金属膜。通过氢等离子体处理来调整底层金属膜的表面状态。通过氢等离子体处理，下面的金属膜的表面被氢化并进行溅射蚀刻，从而去除吸附在下面的金属膜的表面上的无序的膜和污染物。接下来，通过使用有机铝化合物如DMAH的化学气相沉积工艺将铝沉积在下面的金属膜上。接触孔可以有效地填充铝。

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