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    • 5. 发明申请
    • Semiconductor device and method of fabricating the same
    • 半导体装置及其制造方法
    • US20050191817A1
    • 2005-09-01
    • US11066227
    • 2005-02-25
    • Toshiaki KomukaiHideaki Harakawa
    • Toshiaki KomukaiHideaki Harakawa
    • H01L21/28H01L21/3205H01L21/336H01L29/423H01L29/49H01L29/78
    • H01L29/4983H01L29/665H01L29/6653H01L29/6656H01L29/6659
    • According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a gate electrode formed on the substrate via a gate insulating film and containing silicon, an insulating offset spacer formed on a side surface of the gate electrode and having an upper surface lower than an upper surface of the gate electrode, an insulating sidewall spacer formed on an upper side surface of the gate electrode and on a side surface of the offset spacer by using a material different from the offset spacer, a lightly doped impurity diffusion layer formed in the semiconductor substrate so as to sandwich the gate electrode, a heavily doped impurity diffusion layer formed in the semiconductor substrate in a position deeper than the lightly doped impurity diffusion layer, so as to sandwich the gate electrode and sidewall spacer, and a silicide film formed on the gate electrode.
    • 根据本发明的一个方面,提供了一种半导体器件,其包括半导体衬底,通过栅极绝缘膜形成在衬底上并含有硅的栅电极,形成在栅电极的侧表面上的绝缘偏移间隔物,并且具有 通过使用与偏移间隔物不同的材料,形成在栅电极的上侧表面上且在偏置间隔物的侧表面上的绝缘侧壁间隔物,轻掺杂杂质 扩散层,形成在半导体衬底中以将栅电极夹在中间,形成在半导体衬底中的比掺杂稀土杂质扩散层更深的位置的重掺杂杂质扩散层,以夹持栅电极和侧壁间隔,以及 形成在栅电极上的硅化物膜。
    • 6. 发明授权
    • Semiconductor device comprising transistor and capacitor and method of manufacturing the same
    • 包括晶体管和电容器的半导体器件及其制造方法
    • US07858465B2
    • 2010-12-28
    • US12031297
    • 2008-02-14
    • Toshiaki KomukaiHideaki Harakawa
    • Toshiaki KomukaiHideaki Harakawa
    • H01L21/8238
    • H01L27/0629H01L28/60H01L29/7833
    • A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.
    • 根据本发明实施例的半导体器件包括:晶体管,包括由沉积在衬底上的绝缘层形成的栅极绝缘体和由沉积在绝缘层上的电极层形成的栅电极; 电容器,包括由电极层形成的第一电容器电极,形成在第一电容器电极上的第一电容器绝缘体,形成在第一电容器绝缘体上的第二电容器电极,形成在第二电容器电极上的第二电容器绝缘体,以及第三电容器绝缘体 电容器电极形成在第二电容绝缘体上; 以及与晶体管的接触插塞接触的线路图案,第一电容器电极的接触插头,第二电容器电极的接触插塞和第三电容器电极。