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1. 发明申请

US20120105679A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI-ANGLE VIDEO SYSTEM 有权
标题翻译：半导体集成电路和多角度视频系统
公开(公告)号：US20120105679A1
公开(公告)日：2012-05-03
申请号：US13274324
申请日：2011-10-15
申请人： Hiroshi OSUGA , Takaaki Suzuki , Atsushi Kiuchi , Kazuhide Kawade , Hiroyuki Hamasaki
发明人： Hiroshi OSUGA , Takaaki Suzuki , Atsushi Kiuchi , Kazuhide Kawade , Hiroyuki Hamasaki
IPC分类号： H04N5/217 , H04N5/76
CPC分类号： G06T5/006 , G06T2200/28 , G06T2207/10004 , H04N5/2173 , H04N5/23238 , H04N5/247 , H04N5/357 , H04N5/3572 , H04N5/77 , H04N5/907
摘要： The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.
摘要翻译：提供本发明以在将由多个摄像机捕获的图像数据存储到半导体存储器的情况下减少总线上的负载。对于半导体集成电路，可以耦合多个摄像机和半导体存储器。半导体集成电路包括多个第一接口，第二接口，总线和多个图像处理模块。图像处理模块包括对预先指定区域中的图像数据进行失真校正的处理，并且经过失真校正的区域中的图像数据经由总线和第二接口写入半导体存储器。通过从图像处理模块中的失真校正对象中排除预先指定区域之外的图像数据，减少了传送到半导体存储器的图像数据量。

2. 发明授权

US09071750B2 Semiconductor integrated circuit and multi-angle video system 有权
标题翻译：半导体集成电路和多角度视频系统
公开(公告)号：US09071750B2
公开(公告)日：2015-06-30
申请号：US13274324
申请日：2011-10-15
申请人： Hiroshi Osuga , Takaaki Suzuki , Atsushi Kiuchi , Kazuhide Kawade , Hiroyuki Hamasaki
发明人： Hiroshi Osuga , Takaaki Suzuki , Atsushi Kiuchi , Kazuhide Kawade , Hiroyuki Hamasaki
IPC分类号： H04N5/76 , H04N7/18 , H04L12/50 , H04N5/232 , H04N5/247 , H04N5/357 , H04N5/77 , H04N5/907
CPC分类号： G06T5/006 , G06T2200/28 , G06T2207/10004 , H04N5/2173 , H04N5/23238 , H04N5/247 , H04N5/357 , H04N5/3572 , H04N5/77 , H04N5/907
摘要： The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.
摘要翻译：提供本发明以在将由多个摄像机捕获的图像数据存储到半导体存储器的情况下减少总线上的负载。对于半导体集成电路，可以耦合多个摄像机和半导体存储器。半导体集成电路包括多个第一接口，第二接口，总线和多个图像处理模块。图像处理模块包括对预先指定区域中的图像数据进行失真校正的处理，并且经过失真校正的区域中的图像数据经由总线和第二接口写入半导体存储器。通过从图像处理模块中的失真校正对象中排除预先指定区域之外的图像数据，减少了传送到半导体存储器的图像数据量。

3. 发明授权

US07363466B2 Microcomputer 失效
标题翻译：微电脑
公开(公告)号：US07363466B2
公开(公告)日：2008-04-22
申请号：US11354622
申请日：2006-02-14
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F15/76 , G06F9/00 , G06F13/00
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.
摘要翻译：内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。由此，CPU核心2可以将来自内置存储器的两个数据值同时传送到DSP引擎3。此外，第三总线XAB和XDB以及第二总线YAB和YDB也与要外部接口的第一总线IAB和IDB分开，并且CPU核心2可以与访问第二存储器4和6并行地访问外部存储器和第一存储器5和7。

4. 发明授权

US06889240B2 Data processing device having a central processing unit and digital signal processing unit 失效
标题翻译：具有中央处理单元和数字信号处理单元的数据处理装置
公开(公告)号：US06889240B2
公开(公告)日：2005-05-03
申请号：US10694771
申请日：2003-10-29
申请人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F5/01 , G06F7/00 , G06F7/76 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38 , G06F15/78 , G06F17/10 , G06F7/38
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043
摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.
摘要翻译：在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

5. 发明授权

US06185212B2 ATM cell processing apparatus 失效
标题翻译： ATM信元处理装置
公开(公告)号：US06185212B2
公开(公告)日：2001-02-06
申请号：US09056770
申请日：1998-04-08
申请人： Kenichi Sakamoto , Akio Makimoto , Akihiko Takase , Norihiko Moriwaki , Atsushi Kiuchi
发明人： Kenichi Sakamoto , Akio Makimoto , Akihiko Takase , Norihiko Moriwaki , Atsushi Kiuchi
IPC分类号： H04L1228
CPC分类号： H04L49/254 , H04L49/30 , H04L2012/5681
摘要： An ATM cell processing apparatus including a DRAM for a frame producing buffer of a frame producing unit. In order to absorb the anisotropy of the access rate of the DRAM access, the random access mode of the DRAM access is always used. To compensate a drop in access rate in this case, the DRAM is arranged is an array form and each cell is divided. Resultant partial cell data are written into and read from respective DRAM banks in order. As a result, a fast cell buffer having a large capacity can be formed. The present cell buffer can be applied to a FIFO and the like as well.
摘要翻译：一种ATM信元处理装置，包括用于帧产生单元的帧产生缓冲器的DRAM。为了吸收DRAM访问的访问速率的各向异性，始终使用DRAM访问的随机存取模式。为了补偿这种情况下的访问速率的下降，DRAM被排列成阵列形式，并且每个单元被分割。所产生的部分单元数据按顺序写入和从相应的DRAM存储体读取。结果，可以形成具有大容量的快速电池缓冲器。本单元缓冲器也可以应用于FIFO等。

6. 发明授权

US4896104A Digital peak and valley detector 失效
标题翻译：数字峰谷检测器
公开(公告)号：US4896104A
公开(公告)日：1990-01-23
申请号：US311161
申请日：1989-02-15
申请人： Chandravadan N. Patel , Richard Wm. Blasco , Atsushi Kiuchi , Hiromitsu Inada
发明人： Chandravadan N. Patel , Richard Wm. Blasco , Atsushi Kiuchi , Hiromitsu Inada
IPC分类号： G06F7/02 , G01R19/04
CPC分类号： G01R19/04
摘要： A digital peak and valley detector including a peak value address register, a valley value address register, a peak value data register, a valley value data register, a peak comparator for comparing the value stored in the peak value data register with value data contained in the digital signal applied to the digital peak and valley detector and for causing the greater of the two to be stored in the peak value data register while simultaneously storing the address in the peak value address register and a valley comparator for comparing the valley value contained in the valley value data register with the value data contained in the digital signal applied to the digital peak and valley detector for determining which is less and for causing the value and the address of the smaller of the two to be stored respectively in the valley value data and the valley value address registers.
摘要翻译：数字峰谷检测器，包括峰值地址寄存器，谷值地址寄存器，峰值数据寄存器，谷值数据寄存器，用于将存储在峰值数据寄存器中的值与包含在其中的值数据进行比较的峰值比较器数字信号施加到数字峰谷检测器，并使两个中的较大值存储在峰值数据寄存器中，同时将地址存储在峰值地址寄存器和谷比较器中，用于比较包含在谷数值数据寄存器，其中包含在数字信号中的数值数据被加到数字峰谷检测器，用于确定哪一个较小，并且使两个中较小的值的值和地址分别存储在谷值数据中和谷值地址寄存器。

7. 发明授权

US4809206A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US4809206A
公开(公告)日：1989-02-28
申请号：US87346
申请日：1987-08-20
申请人： Atsushi Kiuchi , Kenji Kaneko , Jun Ishida , Tetsuya Nakagawa , Yoshimune Hagiwara , Hirotada Ueda
发明人： Atsushi Kiuchi , Kenji Kaneko , Jun Ishida , Tetsuya Nakagawa , Yoshimune Hagiwara , Hirotada Ueda
IPC分类号： G06F9/34 , G06F7/544 , G06F12/02 , G06F17/10 , H03H17/02 , G06F7/38
CPC分类号： G06F7/5443
摘要： This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.Contrivances are made in order to set the number of a plurality of data that are stored in the data memory for repetition of use, to an arbitrary value.
摘要翻译：本发明涉及诸如数字信号处理器的信息处理设备，并且特别适用于数字滤波器。从初始值数据到与数字滤波器的滤波系数相关的最终值数据的多个数据被存储在数据存储器中，并且通过地址运算单元的增量操作被依次读出。数据运算单元依次执行依次读出的多个数据和顺序输入的数字输入信号的乘积和/或和运算，进行数字信号处理。该信息处理装置特别地具有如下装置：当访问地址从初始值开始时，由于增量操作而超过最终值并达到返回地址，自动将访问地址返回到初始值。因此，可以重复使用存储在数据存储器中的多个数据。为了将存储在用于重复使用的数据存储器中的多个数据的数量设置为任意值，进行了操作。

8. 发明授权

US07069423B2 Microcomputer 失效
公开(公告)号：US07069423B2
公开(公告)日：2006-06-27
申请号：US10201402
申请日：2002-07-22
申请人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Hiroshi Ohsuga , Atsushi Kiuchi , Hironobu Hasegawa , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F9/30
CPC分类号： G06F9/3893 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/3017 , G06F9/345 , G06F9/3552 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/3877 , G06F15/7817
摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

9. 发明授权

US06505295B1 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06505295B1
公开(公告)日：2003-01-07
申请号：US09367536
申请日：1999-08-16
申请人： Mitsuru Hiraki , Atsushi Kiuchi , Kesami Hagiwara
发明人： Mitsuru Hiraki , Atsushi Kiuchi , Kesami Hagiwara
IPC分类号： G06F940
CPC分类号： G06F9/381 , G06F9/325
摘要： To provide a data processing apparatus equipped with a control means to reduce the power required for memory accessing, in spite of the unavailability of a repeat instruction, by reading instructions reiteratively from a small scale buffer in loop processing. Also to provide a data processing apparatus equipped with a means to opt to apply, or not to apply, control to read instructions, that have to be executed reiteratively in loop processing, out of a small scale buffer reiteratively. If, as a result of execution of an instruction to alter the content of a certain register prior to a series of instructions to be executed reiteratively, the register satisfies a specific condition, the series of instructions to be executed repeatedly are read out of a small scale buffer reiteratively. A data processing apparatus equipped with a control means to reduce the power required for memory accessing, in spite of the unavailability of a repeat instruction, by reading instructions reiteratively from a small scale buffer in loop processing can be provided. Also a data processing apparatus equipped with a means to opt to apply, or not to apply, control to read instructions, that have to be executed reiteratively in loop processing, out of a small scale buffer reiteratively can be provided.
摘要翻译：为了提供一种配备有控制装置的数据处理装置，尽管重复指令不可用，通过在循环处理中从小规模缓冲器重复读取指令来减少存储器访问所需的功率。还提供一种数据处理装置，其配备有选择适用于或不应用控制读取必须在循环处理中重复执行的指令的装置，重复地从小规模缓冲器中执行。如果由于在一系列要执行的指令之前执行改变某个寄存器的内容的指令，重复地，寄存器满足特定条件，重复执行的一系列指令被重复地从小规模缓冲器中读出.A数据可以提供配备有控制装置的处理装置，尽管重复指令不可用，通过在循环处理中从小规模缓冲器重复读取指令来减少存储器访问所需的功率。另外，可以提供一种数据处理装置，该装置具有选择适用于或不应用控制读取必须在循环处理中重复执行的指令的装置。

10. 发明授权

US06434691B1 Cell phones with instruction pre-fetch buffers allocated to low bit address ranges and having validating flags 有权
公开(公告)号：US06434691B1
公开(公告)日：2002-08-13
申请号：US09824186
申请日：2001-04-03
申请人： Yasuyuki Murakami , Shigezumi Matsui , Kunihiko Nishiyama , Atsushi Kiuchi , Yuichi Takitsune
发明人： Yasuyuki Murakami , Shigezumi Matsui , Kunihiko Nishiyama , Atsushi Kiuchi , Yuichi Takitsune
IPC分类号： G06F938
摘要： In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of instruction buffers, flags each specific to each of instruction buffers, and a buffer controller circuit. The buffer controller circuit may allocate one of specific values that plural lower bits of an instruction address may take to each of the instruction buffers, and prefetch instructions to the instruction buffers each corresponding to a respective addresses designated to by the plural lower bits, from the address following a predetermined fetch address. The constitution for instruction prefetch as above may be implemented in a simpler manner than the controlling structure using address tags of a cache memory or the controlling structure using read-write pointer based on the counter in FIFO buffers.

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