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1. 发明授权

US06463066B2 ATM switch 失效
标题翻译： ATM交换机
公开(公告)号：US06463066B2
公开(公告)日：2002-10-08
申请号：US09797696
申请日：2001-03-05
申请人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
发明人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
IPC分类号： H04J324
CPC分类号： H04L49/108 , H04Q11/0478
摘要： Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.
摘要翻译：提供了一种高吞吐量大容量ATM交换机，其中在将DRAM用作ATM交换机的小区缓冲器的情况下产生的存储器访问时间和数据输出延迟时间的变化被吸收。为了实现这一点，ATM交换机包括使用用于存储单元的DRAM的第一存储器，使用SRAM的第二存储器，用于在将单元传送到第一存储器之前切换和临时存储单元;以及控制器，用于产生写/ 用于第一和第二存储器的定时信号。控制器产生用于第二存储器的读取地址和定时信号，并且基于第一存储器的存取地址来考虑第一存储器的存取时间或延迟时间的变化的写入地址和定时信号，从而在目的地输出将单元切换并存储在第二存储器中，然后存储在第一存储器中。

2. 发明授权

US06185212B2 ATM cell processing apparatus 失效
标题翻译： ATM信元处理装置
公开(公告)号：US06185212B2
公开(公告)日：2001-02-06
申请号：US09056770
申请日：1998-04-08
申请人： Kenichi Sakamoto , Akio Makimoto , Akihiko Takase , Norihiko Moriwaki , Atsushi Kiuchi
发明人： Kenichi Sakamoto , Akio Makimoto , Akihiko Takase , Norihiko Moriwaki , Atsushi Kiuchi
IPC分类号： H04L1228
CPC分类号： H04L49/254 , H04L49/30 , H04L2012/5681
摘要： An ATM cell processing apparatus including a DRAM for a frame producing buffer of a frame producing unit. In order to absorb the anisotropy of the access rate of the DRAM access, the random access mode of the DRAM access is always used. To compensate a drop in access rate in this case, the DRAM is arranged is an array form and each cell is divided. Resultant partial cell data are written into and read from respective DRAM banks in order. As a result, a fast cell buffer having a large capacity can be formed. The present cell buffer can be applied to a FIFO and the like as well.
摘要翻译：一种ATM信元处理装置，包括用于帧产生单元的帧产生缓冲器的DRAM。为了吸收DRAM访问的访问速率的各向异性，始终使用DRAM访问的随机存取模式。为了补偿这种情况下的访问速率的下降，DRAM被排列成阵列形式，并且每个单元被分割。所产生的部分单元数据按顺序写入和从相应的DRAM存储体读取。结果，可以形成具有大容量的快速电池缓冲器。本单元缓冲器也可以应用于FIFO等。

3. 发明授权

US06249524B1 Cell buffer memory for a large capacity and high throughput ATM switch 失效
标题翻译：用于大容量和高吞吐量ATM交换机的单元缓冲存储器
公开(公告)号：US06249524B1
公开(公告)日：2001-06-19
申请号：US09044171
申请日：1998-03-19
申请人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
发明人： Norihiko Moriwaki , Kenichi Sakamoto , Akihiko Takase , Akio Makimoto , Kazumasa Yanagisawa
IPC分类号： H04J324
CPC分类号： H04L49/108 , H04Q11/0478
摘要： Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.
摘要翻译：提供了一种高吞吐量大容量ATM交换机，其中在将DRAM用作ATM交换机的小区缓冲器的情况下产生的存储器访问时间和数据输出延迟时间的变化被吸收。为了实现这一点，ATM交换机包括使用用于存储单元的DRAM的第一存储器，使用SRAM的第二存储器，用于在将单元传送到第一存储器之前切换和临时存储单元;以及控制器，用于产生写/ 用于第一和第二存储器的定时信号。控制器产生用于第二存储器的读取地址和定时信号，并且基于第一存储器的存取地址来考虑第一存储器的存取时间或延迟时间的变化的写入地址和定时信号，从而在目的地输出将单元切换并存储在第二存储器中，然后存储在第一存储器中。

4. 发明授权

US06977941B2 Shared buffer type variable length packet switch 失效
标题翻译：共享缓冲区类型可变长度分组交换机
公开(公告)号：US06977941B2
公开(公告)日：2005-12-20
申请号：US09791791
申请日：2001-02-26
申请人： Masami Takahashi , Akio Makimoto , Takahiko Kozaki , Takayuki Kanno , Yasuo Oginuma , Kaori Nakayama , Mitsuhiro Wada , Norihiko Moriwaki , Masumi Fukano , Yusho Futami
发明人： Masami Takahashi , Akio Makimoto , Takahiko Kozaki , Takayuki Kanno , Yasuo Oginuma , Kaori Nakayama , Mitsuhiro Wada , Norihiko Moriwaki , Masumi Fukano , Yusho Futami
IPC分类号： H04L12/56 , G06F12/00
CPC分类号： H04L49/103 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/40
摘要： A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.
摘要翻译：一种分组交换机，具有以固定长度数据块单位为基础将从每个输入线路接收的可变长度分组写入共享缓冲存储器的结构，其中缓冲器控制器为每个输入线路形成输入队列，并且当最后数据可变长度分组的块被登记在输入队列中，将用于输入队列的链接地址列表链接到对应于一个或多个分组目的地输出线的一个或多个输出队列。

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