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    • 5. 发明授权
    • Output circuit
    • 输出电路
    • US08604844B2
    • 2013-12-10
    • US13195546
    • 2011-08-01
    • Kouichi NishimuraHiromichi OhtsukaToshikazu Murata
    • Kouichi NishimuraHiromichi OhtsukaToshikazu Murata
    • H03K3/00
    • H03K19/018528
    • An output circuit includes a first output transistor disposed between a higher-potential power supply terminal and an external output terminal, a current flowing from the source of the first output transistor to the drain thereof being controlled on the basis of an external input signal; a second output transistor disposed between a lower-potential power supply terminal and the external output terminal, a current flowing from the source of the second output transistor to the drain thereof being controlled on the basis of an external input signal; and a clamping transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output transistor, and a second terminal coupled to the drain of the first output transistor.
    • 输出电路包括设置在高电位电源端子和外部输出端子之间的第一输出晶体管,基于外部输入信号控制从第一输出晶体管的源极到其漏极的电流; 设置在低电位电源端子和外部输出端子之间的第二输出晶体管,基于外部输入信号控制从第二输出晶体管的源极流向其漏极的电流; 以及具有第一端子和控制端子的钳位晶体管,所述第一端子和所述控制端子耦合到所述第一输出晶体管的栅极,以及耦合到所述第一输出晶体管的漏极的第二端子。
    • 7. 发明授权
    • Transmitter circuit, transmission circuit and driver unit
    • 变送器电路,传输电路和驱动单元
    • US08421727B2
    • 2013-04-16
    • US13436640
    • 2012-03-30
    • Akio HosokawaKouichi Nishimura
    • Akio HosokawaKouichi Nishimura
    • G09G3/36H03K19/094H03K3/00H03B1/00
    • G09G3/20G09G2310/0267G09G2310/0275G09G2370/08H03K5/1534H04L25/0272H04L25/0286
    • A transmitter circuit includes a driver circuit including a non-inverting output terminal and an inverting output terminal for outputting a signal current, which has a loop direction that changes based upon an input signal, to the non-inverting output terminal and the inverting output terminal and an output-waveform control circuit for detecting a waveform edge of the input signal and responding by increasing the signal current temporarily. The output-waveform control circuit includes a first inverter circuit receiving a non-inverted input signal, a first capacitor including one end connected to an output terminal of the first inverter circuit and another end connected to the inverting output terminal, a second inverter circuit receiving an inverted input signal, and a second capacitor including one end connected to an output terminal of the second inverter circuit and another end connected to the non-inverting output terminal.
    • 发射机电路包括:驱动器电路,包括非反相输出端子和反相输出端子,用于将具有基于输入信号改变的环路方向的信号电流输出到非反相输出端子和反相输出端子 以及输出波形控制电路,用于检测输入信号的波形边缘,并通过临时增加信号电流进行响应。 输出波形控制电路包括接收非反相输入信号的第一反相器电路,第一电容器,其包括连接到第一反相器电路的输出端的一端和连接到反相输出端的另一端,第二反相器电路接收 反相输入信号和第二电容器,其包括连接到第二反相器电路的输出端的一端和连接到非反相输出端的另一端。
    • 8. 发明申请
    • INFORMATION SYSTEM, CONTROL DEVICE, METHOD OF MANAGING VIRTUAL NETWORK, AND PROGRAM
    • 信息系统,控制设备,虚拟网络管理方法和程序
    • US20130003745A1
    • 2013-01-03
    • US13634538
    • 2011-03-22
    • Kouichi Nishimura
    • Kouichi Nishimura
    • H04L12/56
    • H04L12/56H04L12/4641H04L45/02
    • An information system includes a plurality of forwarding nodes having a packet processing unit that performs processing of a received packet using a processing rule conforming to the received packet; and a control device causing plurality of forwarding nodes to operate as a virtual network by setting a processing rule in the forwarding nodes. The control device includes a virtual network path information storage unit that stores a correspondence relationship between the virtual network and a forwarding path configured by the forwarding nodes; and a virtual network control unit that identifies a virtual network affected by a change in a state of any forwarding node among the plurality of forwarding nodes, by referring to the virtual network path information storage unit.
    • 一种信息系统,包括具有分组处理单元的多个转发节点,所述分组处理单元使用符合所接收到的分组的处理规则来执行接收分组的处理; 以及控制装置,通过在转发节点中设置处理规则,使多个转发节点作为虚拟网络进行操作。 控制装置包括存储虚拟网络与由转发节点配置的转发路径之间的对应关系的虚拟网络路径信息存储单元; 以及虚拟网络控制单元,通过参照虚拟网络路径信息存储单元来识别受到多个转发节点中的任何转发节点的状态的改变的影响的虚拟网络。
    • 10. 发明申请
    • Output circuit using analog amplifier
    • 输出电路采用模拟放大器
    • US20100271129A1
    • 2010-10-28
    • US12662626
    • 2010-04-26
    • Kouichi Nishimura
    • Kouichi Nishimura
    • H03F3/45
    • H03F3/45475H03F3/3022H03F2203/30078H03F2203/30111H03F2203/45528H03F2203/45631
    • An output circuit includes an analog amplifier circuit including a differential amplifier stage configured to receive an input voltage, and first to nth output systems (n is a natural number more than 1); first to nth output nodes; an output pad; and first to nth electrostatic protection resistances. An ith output system (i is a natural number between 2 and n) of the first to nth output systems includes an ith PMOS transistor having a drain connected with the ith output node of the first to nth output nodes and a gate connected with a first output of the differential amplifier stage; and an ith NMOS transistor having a drain connected with the ith output node and a gate connected with a second output of the differential amplifier stage. The first to nth electrostatic protection resistances are respectively connected between the first to nth output nodes and the output pad.
    • 输出电路包括:模拟放大器电路,包括被配置为接收输入电压的差分放大器级,以及第一至第n输出系统(n是大于1的自然数); 第一到第n个输出节点; 输出板 和第一至第n静电保护电阻。 第一至第n输出系统中的第i个输出系统(i是2和n之间的自然数)包括具有与第一至第n输出节点的第i个输出节点连接的漏极的第i个PMOS晶体管,以及与第一个 输出差分放大器级; 以及具有与第i个输出节点连接的漏极和与差分放大器级的第二输出端连接的栅极的第i个NMOS晶体管。 第一至第n静电保护电阻分别连接在第一至第N输出节点和输出板之间。