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1. 发明授权

US08605485B2 Non-volatile semiconductor storage device and forming method 有权
标题翻译：非易失性半导体存储器件及其形成方法
公开(公告)号：US08605485B2
公开(公告)日：2013-12-10
申请号：US13350067
申请日：2012-01-13
申请人： Hiroshi Kanno , Takafumi Shimotori , Yoichi Minemura , Takahiko Sasaki , Takayuki Tsukamoto
发明人： Hiroshi Kanno , Takafumi Shimotori , Yoichi Minemura , Takahiko Sasaki , Takayuki Tsukamoto
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0083
摘要： According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.
摘要翻译：根据一个实施例，控制单元从多条第一行为每N条线选择第一行。 N是大于或等于1的整数。控制单元将多个选择的第一行设置为选择电位，并且在第一定时将至少与多个选择的第一行相邻的未选择的第一行的电位进行固定。控制单元使第一定时后的第二定时使多选第一行处于浮动状态。控制单元从多条第二行中选择一条第二行，并在第二定时之后的第三定时将一条第二行设置成一个形成电位。

2. 发明申请

US20120224411A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND FORMING METHOD 有权
标题翻译：非挥发性半导体存储器件和形成方法
公开(公告)号：US20120224411A1
公开(公告)日：2012-09-06
申请号：US13350067
申请日：2012-01-13
申请人： Hiroshi KANNO , Takafumi Shimotori , Yoichi Minemura , Takahiko Sasaki , Takayuki Tsukamoto
发明人： Hiroshi KANNO , Takafumi Shimotori , Yoichi Minemura , Takahiko Sasaki , Takayuki Tsukamoto
IPC分类号： G11C11/21
CPC分类号： G11C13/0002 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0083
摘要： According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.
摘要翻译：根据一个实施例，控制单元从多条第一行为每N条线选择第一行。 N是大于或等于1的整数。控制单元将多个选择的第一行设置为选择电位，并且在第一定时将至少与多个选择的第一行相邻的未选择的第一行的电位进行固定。控制单元使第一定时后的第二定时使多选第一行处于浮动状态。控制单元从多条第二行中选择一条第二行，并在第二定时之后的第三定时将一条第二行设置成一个形成电位。

3. 发明授权

US08279655B2 Non-volatile semiconductor memory device and method of controlling non-volatile semiconductor memory device 有权
标题翻译：非挥发性半导体存储器件及非易失性半导体存储器件的控制方法
公开(公告)号：US08279655B2
公开(公告)日：2012-10-02
申请号：US12885013
申请日：2010-09-17
申请人： Hiroshi Kanno , Takayuki Tsukamoto , Takahiko Sasaki , Takafumi Shimotori
发明人： Hiroshi Kanno , Takayuki Tsukamoto , Takahiko Sasaki , Takafumi Shimotori
IPC分类号： G11C11/00 , G11C29/04
CPC分类号： G11C8/10 , G11C13/0007 , G11C13/0069 , G11C29/50016 , G11C2013/0083 , G11C2213/31 , G11C2213/32 , G11C2213/72
摘要： According to an embodiment, there are provided a non-volatile semiconductor memory device includes: a memory cell array; a control circuit performing a series of operations to each memory cell and determining, as a defective memory cell, a memory cell whose data retention property does not satisfy a criteria, the series of operations including an operation applying a first bias to the memory cell in a forward direction, and including an operation thereafter applying a second bias to the memory cell in a reverse direction; a storage unit storing an address of the defective memory cell; and an address control unit performing a control to avoid storing data in the defective memory cell whose address is stored in the storage unit.
摘要翻译：根据实施例，提供了一种非易失性半导体存储器件，包括：存储单元阵列; 对每个存储单元执行一系列操作的控制电路，并且确定其数据保持特性不满足标准的存储单元作为缺陷存储单元，所述一系列操作包括对存储单元施加第一偏置的操作并且包括在相反方向上向存储单元施加第二偏置的操作; 存储单元，存储有缺陷的存储单元的地址; 以及地址控制单元，执行控制以避免将数据存储在其地址存储在存储单元中的有缺陷的存储单元中。

4. 发明授权

US08576605B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08576605B2
公开(公告)日：2013-11-05
申请号：US13051766
申请日：2011-03-18
申请人： Takahiko Sasaki
发明人： Takahiko Sasaki
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C8/08 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2029/1202 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array configured by plural memory cells each including a variable resistor and each provided between first and second lines. A control circuit applies to a memory cell through the first and second lines a writing voltage for writing data or a reading voltage for reading data. A sense amplifier circuit senses data retained in a memory cell based on a current flowing through the first line. In a data writing operation, the control circuit applies a writing voltage to each of n number of memory cells configuring one unit such that the memory cells may be supplied with different resistance values. In a data reading operation, the sense amplifier circuit compares level relationship of the resistance values of n number of memory cells configuring one unit and reads out n! patterns of data from the one unit.
摘要翻译：根据实施例的非易失性半导体存储器件包括由多个存储单元构成的存储单元阵列，每个存储单元包括可变电阻器，每个存储单元设置在第一和第二线路之间。控制电路通过第一和第二行向存储器单元施加写入数据的写入电压或用于读取数据的读取电压。感测放大器电路基于流过第一线路的电流来感测保存在存储器单元中的数据。在数据写入操作中，控制电路对构成一个单元的n个存储单元中的每一个施加写入电压，使得可以向存储单元提供不同的电阻值。在数据读取操作中，读出放大器电路比较构成一个单元的n个存储单元的电阻值的电平关系，并读出n！来自一个单位的数据模式。

5. 发明授权

US08422269B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08422269B2
公开(公告)日：2013-04-16
申请号：US13033151
申请日：2011-02-23
申请人： Takahiko Sasaki , Tomonori Kurosawa
发明人： Takahiko Sasaki , Tomonori Kurosawa
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0026 , G11C13/004 , G11C13/0064 , G11C2013/0083 , G11C2213/72
摘要： A control circuit applies a first voltage to selected one of first lines and applies a second voltage having a voltage value smaller than that of the first voltage to selected one of second lines, such that a certain potential difference is applied across a memory cell disposed at an intersection of the selected one of the first lines and the selected one of the second lines. A current limiting circuit sets a compliance current defining an upper limit of a cell current flowing in the memory cell, and controls such that the cell current flowing in the memory cell does not exceed the compliance current. The current limiting circuit comprises a current generating circuit and a first current mirror circuit. The current generating circuit generates a first current having a current value equal to a current value of the cell current at a certain timing multiplied by a certain constant. The first current mirror circuit mirrors the first current to a current path supplying the first voltage to the first lines.
摘要翻译：控制电路将第一电压施加到所选择的第一行中的一个，并将具有小于第一电压的电压值的第二电压施加到所选择的第二行中的一个，使得在设置在第二行的存储单元上施加一定的电位差所选择的第一行和所选择的第二行之一的交集。电流限制电路设定限定在存储单元中流动的电池电流的上限的顺从电流，并进行控制使得在存储单元中流动的电池电流不超过顺应性电流。限流电路包括电流产生电路和第一电流镜电路。电流产生电路产生具有等于电池电流当前值的电流值的第一电流，该电流值以某一定时乘以一定常数。第一电流镜电路将第一电流反射到向第一线提供第一电压的电流路径。

6. 发明授权

US08270247B2 Word line driving circuit and semiconductor storage device 有权
标题翻译：字线驱动电路和半导体存储器件
公开(公告)号：US08270247B2
公开(公告)日：2012-09-18
申请号：US12885305
申请日：2010-09-17
申请人： Takahiko Sasaki
发明人： Takahiko Sasaki
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C11/418
摘要： According to one embodiment, a word line driving circuit includes a driver and a booster circuit. The driver drives a word line based on an output of an inverter. The booster circuit connects a boosting capacitor to a source side of a P-channel field effect transistor of the inverter to boost the potential of the word line.
摘要翻译：根据一个实施例，字线驱动电路包括驱动器和升压电路。驱动器根据变频器的输出驱动字线。升压电路将升压电容器连接到逆变器的P沟道场效应晶体管的源极侧，以提高字线的电位。

7. 发明授权

US08331177B2 Resistance semiconductor memory device having a bit line supplied with a compensating current based on a leak current detected during a forming operation 有权
标题翻译：电阻半导体存储器件，其具有基于在成形操作期间检测到的漏电流而提供有补偿电流的位线
公开(公告)号：US08331177B2
公开(公告)日：2012-12-11
申请号：US13051110
申请日：2011-03-18
申请人： Takahiko Sasaki
发明人： Takahiko Sasaki
IPC分类号： G11C29/00
CPC分类号： G11C5/148 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2013/0083 , G11C2213/72
摘要： A semiconductor memory device includes a memory cell array, a first control circuit, and a second control circuit. The first control circuit is configured to apply a first voltage to a selected first line. The second control circuit is configured to apply a second voltage having a voltage value higher than that of the first voltage to a selected second line. The first control circuit includes a detecting circuit. The detecting circuit is configured to detect a leak current to flow from the second line to the first line through a memory cell during a forming operation for bringing the memory cell into a state that allows the memory cell to shift between a high resistance state and a low resistance state. The second control circuit includes a current supply circuit, and a compensating circuit. The current supply circuit is configured to supply a constant current to the second line during the forming operation. The compensating circuit is configured to supply a compensating current having the same current value as that of the leak current to the second line during the forming operation based on the leak current detected by the detecting circuit.
摘要翻译：半导体存储器件包括存储单元阵列，第一控制电路和第二控制电路。第一控制电路被配置为将第一电压施加到所选择的第一线。第二控制电路被配置为将具有高于第一电压的电压值的第二电压施加到所选择的第二线。第一控制电路包括检测电路。检测电路被配置为在形成操作期间检测泄漏电流从第二线路流过第一线路，以使存储器单元进入允许存储器单元在高电阻状态和低电阻状态。第二控制电路包括电流源电路和补偿电路。电流供给电路被配置为在成形操作期间向第二线路提供恒定电流。补偿电路被配置为基于由检测电路检测到的泄漏电流，在成形操作期间将具有与漏电流相同的电流值的补偿电流提供给第二线。

8. 发明申请

US20100302831A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100302831A1
公开(公告)日：2010-12-02
申请号：US12790497
申请日：2010-05-28
申请人： Yasuhisa Takeyama , Osamu Hirabayashi , Takahiko Sasaki , Yuki Fujimura
发明人： Yasuhisa Takeyama , Osamu Hirabayashi , Takahiko Sasaki , Yuki Fujimura
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C11/412
摘要： A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.
摘要翻译：静态随机存取存储器（SRAM）的存储单元包括一对驱动晶体管，一对负载晶体管，一对只写转移晶体管，一对只读传输晶体管，一对只读驱动器晶体管和一对列选择晶体管。存储单元还包括字线，一对写位线，一对读位线和列选择线。

9. 发明申请

US20050189613A1 Semiconductor device as electrically programmable fuse element and method of programming the same 有权
标题翻译：半导体器件作为电可编程熔丝元件及其编程方法
公开(公告)号：US20050189613A1
公开(公告)日：2005-09-01
申请号：US10851143
申请日：2004-05-24
申请人： Nobuaki Otsuka , Takahiko Sasaki , Shuso Fujii
发明人： Nobuaki Otsuka , Takahiko Sasaki , Shuso Fujii
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/10 , H01L27/108 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.
摘要翻译：在第一和第二端子之间形成熔丝连接。第一和第二端子和熔丝链路具有多晶硅层和形成在多晶硅层上并且包含金属元件的层。熔丝链的至少一部分是非晶硅层。

10. 发明授权

US08498141B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08498141B2
公开(公告)日：2013-07-30
申请号：US13051312
申请日：2011-03-18
申请人： Takahiko Sasaki , Mizuki Uda
发明人： Takahiko Sasaki , Mizuki Uda
IPC分类号： G11C11/00
CPC分类号： G11C16/24
摘要： A memory cell array includes a memory cell having a variable resistance element and disposed between first and second wirings. A control circuit provides a selected first wiring with a first voltage and provide a selected second wiring with a second voltage having a lower voltage value than the first voltage. A current limitation circuit controls a cell current below a first current. It includes a first current generation circuit for storing a cell current at a first point of time and generating a first current of α times the stored cell current. It also includes a second current generation circuit for generating a second current of (β/α) times the cell current at a second point of time. A determination circuit outputs a control signal when the second current exceeds the stored current. The first current generation circuit newly stores a stored current according to the control signal.
摘要翻译：存储单元阵列包括具有可变电阻元件并设置在第一和第二布线之间的存储单元。控制电路为所选择的第一布线提供第一电压，并且向第二布线提供具有比第一电压低的电压值的第二电压。电流限制电路控制低于第一电流的电池电流。它包括第一电流产生电路，用于在第一时间点存储电池电流，并产生第一电流α乘以存储的电池电流。它还包括用于在第二时间点产生电池电流（β/α）的第二电流的第二电流产生电路。当第二电流超过存储电流时，确定电路输出控制信号。第一电流产生电路根据控制信号新存储存储的电流。

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