专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5870039A Code converter, variable length code decoder, and associated methods 失效
标题翻译：代码转换器，可变长度码解码器和相关方法
公开(公告)号：US5870039A
公开(公告)日：1999-02-09
申请号：US877241
申请日：1997-06-17
申请人： Hiroshi Imanishi , Masaki Toyokura
发明人： Hiroshi Imanishi , Masaki Toyokura
IPC分类号： G11B20/10 , H03M7/30 , H03M7/40
CPC分类号： G11B20/10 , H03M7/30 , H03M7/40
摘要： The present invention makes it possible to achieve restoration of decoding processing more intricately in comparison with commonly-used techniques. The present invention increases post-restoration data reliability and is applicable to real-time decoding processing. A variable length code converter of the present invention provides an abnormal code detection signal when a bit-string subjected to conversion corresponds to none of variable length codes that belong in predetermined coding systems. At this time, a controller provides an error signal, and according to the error signal a bit-string is continuously output from a memory which stores bit-strings to be decoded. When the controller detects a header indicative of data partition from an output bit-string of the memory, it cancels the error signal. As a result, bit-string decoding resumes after the detected header.
摘要翻译：与普通技术相比，本发明可以更复杂地实现解码处理的恢复。本发明提高了恢复后数据的可靠性，并且适用于实时解码处理。本发明的可变长度码转换器当经过转换的位串对应于不属于预定编码系统的可变长度码时，提供异常码检测信号。此时，控制器提供误差信号，并且根据误差信号，从存储要解码的位串的存储器连续输出位串。当控制器从存储器的输出位串检测到指示数据分区的头部时，它消除误差信号。结果，在检测到的报头之后，重新开始位串解码。

2. 发明授权

US06501398B2 Variable-length code decoder using barrel shifters and a look-up table 有权
标题翻译：使用桶形移位器和查找表的可变长度码解码器
公开(公告)号：US06501398B2
公开(公告)日：2002-12-31
申请号：US09815269
申请日：2001-03-23
申请人： Masaki Toyokura
发明人： Masaki Toyokura
IPC分类号： H03M700
CPC分类号： H03M7/40 , H03M7/42
摘要： A variable-length code decoder sequentially decodes a series of variable-length codewords included in a bit stream and outputs decoded symbols corresponding to the codewords. The decoder includes an interface section and a decoding section. The interface section accumulates various code lengths of the decoded codewords to obtain a sum. Next, the interface section selects an N-bit contiguous data sequence (where N is a maximum code length of the codewords) from a 2N- or (2N−1)-bit contiguous data sequence, included in the bit stream, in accordance with the sum and outputs the N-bit contiguous data sequence. The decoding section receives the output of the interface section and decodes a codeword included in a combination of the output and a previous output of the interface section by reference to a lookup table, thereby obtaining and outputting a decoded symbol and outputting a code length of the decoded codeword to the interface section.
摘要翻译：可变长度码解码器对包括在比特流中的一系列可变长度码字进行顺序解码，并输出对应于码字的解码符号。解码器包括接口部分和解码部分。接口部分累积解码码字的各种码长以获得和。接下来，接口部分根据比特流中包含的2N或（2N-1）位连续的数据序列，选择N位连续数据序列（其中N是码字的最大码长）并且输出N位连续的数据序列。解码部分接收接口部分的输出，并通过参考查找表对接口部分的输出和先前输出的组合中包括的码字进行解码，从而获得并输出解码符号并输出解码部分的代码长度解码码字到接口部分。

3. 发明授权

US5293596A Multidimensional address generator and a system for controlling the generator 失效
公开(公告)号：US5293596A
公开(公告)日：1994-03-08
申请号：US658154
申请日：1991-02-20
申请人： Masaki Toyokura , Kunitoshi Aono , Toshiyuki Araki
发明人： Masaki Toyokura , Kunitoshi Aono , Toshiyuki Araki
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0207
摘要： A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder. Moreover, data selected by the first multiplexer is added by the adder to data selected by the second multiplexer, and data selected by the third multiplexer is inputted to the first to Nth accumulating registers. Furthermore, a start address is written to the first to Nth accumulating registers when the address generator is activated. Moreover, the first increment is added to the data held in the first accumulating register in each of Cycles 1 to (P.sub.1 -1) and . . . and Cycles (P.sub.N P.sub.N-1 . . . P.sub.2 -1)P.sub.1 +1 to (P.sub.N P.sub.N-1 . . . P.sub.2 P.sub.1 -1), the first increment is added to the data held in the first accumulating register, and a result is written thereto. Additionally, an nth increment (n=2, 3, . . . , N) is added to the data held in the nth accumulating register, and a result is written to the first to nth accumulating registers, every P.sub.n-1 P.sub.n-2 . . . P.sub.1 cycles during Cycles P.sub.n P.sub.n-1 P.sub.n-2 . . . P.sub.1 to (P.sub.n -1)P.sub.n-1 P.sub.n-2 . . . P.sub.1 and so on. The data finally obtained in the first accumulating register is outputted. Consequently, an operation of accessing a plurality of multidimensional data can be performed easily and quickly.

4. 发明授权

US5596518A Orthogonal transform processor 失效
标题翻译：正交变换处理器
公开(公告)号：US5596518A
公开(公告)日：1997-01-21
申请号：US434298
申请日：1995-05-03
申请人： Masaki Toyokura , Kiyoshi Okamoto , Yoshifumi Matsumoto
发明人： Masaki Toyokura , Kiyoshi Okamoto , Yoshifumi Matsumoto
IPC分类号： G06F7/544 , G06F17/14
CPC分类号： G06F17/147 , G06F7/5443
摘要： Stored in each of four coefficient memories are eight elements of each row of a matrix in 4 rows and 8 columns, which matrix consists of absolute values of elements of upper four rows out of an inverse discrete cosine matrix in 8 rows and 8 columns to be subjected to an 8-point IDCT processing. An input element y.sub.ij is supplied in parallel to four multipliers. Each of the four multipliers executes multiplication of an output of the corresponding coefficient memory out of the four coefficient memories, by the input element y.sub.ij. Eight accumulators are disposed for executing, in parallel, accumulation for obtaining eight inner products using results of the four multipliers while restoring signs of the coefficients of the orthogonal transform matrix. An 8-input selector is disposed for successively selecting results of the eight accumulators to supply an inner product w.sub.ij corresponding to the input element y.sub.ij.
摘要翻译：存储在四个系数存储器的每一个中的是四行和八列中矩阵的每一行的八个元素，该矩阵由8行和8列中的反离散余弦矩阵中的上四行的元素的绝对值组成经过8点IDCT处理。输入元素yij并行提供给四个乘法器。四个乘法器中的每一个由输入元件yij执行四个系数存储器中的对应系数存储器的输出的乘法。八个累加器被设置为并行执行累积，以使用四个乘法器的结果来获得八个内积，同时恢复正交变换矩阵的系数的符号。设置8输入选择器，用于连续选择八个累加器的结果，以提供对应于输入元件yij的内积wij。

5. 发明申请

US20080131089A1 Data Recording/Reproducing Device 审中-公开
标题翻译：数据记录/再现装置
公开(公告)号：US20080131089A1
公开(公告)日：2008-06-05
申请号：US11794955
申请日：2006-09-08
申请人： Masaki Toyokura
发明人： Masaki Toyokura
IPC分类号： H04N5/92
CPC分类号： H04N9/8042 , H04N5/85 , H04N21/4147 , H04N21/4341 , H04N21/4385
摘要： A data recording/reproducing device includes a transport stream decoder for decoding a transport stream and outputting a resultant signal; a program stream encoder for obtaining a program stream by encoding the signal output from the transport stream decoder and outputting the program stream; and a system control unit for controlling the transport stream decoder and the program stream encoder to execute TS-PS conversion. In consideration of priority of processing of the TS-PS conversion, the system control unit allows the TS-PS conversion to be executed when both of the transport stream decoder and the program stream encoder are available for the TS-PS conversion.
摘要翻译：数据记录/再现装置包括传输流解码器，用于解码传输流并输出合成信号; 节目流编码器，用于通过对从传输流解码器输出的信号进行编码并输出节目流来获得节目流; 以及用于控制传输流解码器和程序流编码器以执行TS-PS转换的系统控制单元。考虑到TS-PS转换的处理的优先级，当传输流解码器和程序流编码器都可用于TS-PS转换时，系统控制单元允许执行TS-PS转换。

6. 发明授权

US06950462B2 Video encoding apparatus, video encoding method, and frame rate conversion apparatus 失效
标题翻译：视频编码装置，视频编码方法和帧速率转换装置
公开(公告)号：US06950462B2
公开(公告)日：2005-09-27
申请号：US10092725
申请日：2002-03-08
申请人： Akihiro Watabe , Akihiro Otani , Masaki Toyokura
发明人： Akihiro Watabe , Akihiro Otani , Masaki Toyokura
IPC分类号： H04N19/50 , H03M7/36 , H04N19/136 , H04N19/423 , H04N19/426 , H04N19/587 , H04N19/70 , H04B1/66
CPC分类号： H04N19/428 , H04N19/423 , H04N19/61
摘要： When an input picture is inputted to a video interface and stored in a reordering memory, the input time is recorded utilizing a reference time generator and a frame sync signal, and a frame memory to be encoded by an encoding unit is designated using the time information. Therefore, an encoder, which can perform stable encoding even when intervals of vertical sync signals are varied, is realized.
摘要翻译：当将输入图像输入到视频接口并存储在重排序存储器中时，使用参考时间发生器和帧同步信号记录输入时间，并且使用时间信息指定要由编码单元编码的帧存储器。因此，即使在垂直同步信号的间隔变化的情况下也能够进行稳定编码的编码器。

7. 发明授权

US5299320A Program control type vector processor for executing a vector pipeline operation for a series of vector data which is in accordance with a vector pipeline 失效
标题翻译：程序控制类型向量处理器，用于对与矢量流水线相对应的一系列向量数据执行向量流水线操作
公开(公告)号：US5299320A
公开(公告)日：1994-03-29
申请号：US752787
申请日：1991-08-30
申请人： Kunitoshi Aono , Masaki Toyokura , Toshiyuki Araki , Akihiko Ohtani , Hisashi Kodama , Kiyoshi Okamoto
发明人： Kunitoshi Aono , Masaki Toyokura , Toshiyuki Araki , Akihiko Ohtani , Hisashi Kodama , Kiyoshi Okamoto
IPC分类号： G06F9/345 , G06F9/38 , G06F15/78 , G06F9/30
CPC分类号： G06F15/8076 , G06F9/30036 , G06F9/345 , G06F9/3885
摘要： In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction. The data processor executes the pipeline operation for the data outputted from the data memory by being controlled by the program controller, and the program controller detects completion of the pipeline operation performed in response to the vector pipeline instruction a predetermined number of cycles after receiving the end signal, and thereafter, sequentially executes instructions following the vector pipeline instruction.
摘要翻译：在用于执行包括包括用于执行流水线操作的数据处理器的向量流水线指令的多个指令的程序控制类型处理器中，提供了一种程序控制器，其包括程序存储器，程序计数器和解码器，并且还提供有地址生成器和数据存储器。当从程序存储器中读出向量流水线指令并由解码器解码时，程序控制器停止程序计数器并输出起始信号，然后根据向量管线的内容来控制数据处理器的操作指令。数据处理器通过由程序控制器控制从数据存储器输出的数据执行流水线操作，并且程序控制器在接收到结束之后响应于向量流水线指令检测预定数量的循环执行的流水线操作的完成信号，然后依次执行向量流水线指令之后的指令。

8. 发明授权

US07231477B2 Bus controller 有权
标题翻译：总线控制器
公开(公告)号：US07231477B2
公开(公告)日：2007-06-12
申请号：US10802933
申请日：2004-03-18
申请人： Masaki Toyokura
发明人： Masaki Toyokura
IPC分类号： G06F13/14
CPC分类号： G06F13/1605
摘要： A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access request to a common memory. When it is expected from the present cycle number that a limit cycle number is exceeded, the bus controller selects a processing level with which the processing is performed with a smaller cycle number, or performs a control of giving no permission to a non-realtime bus access request. Thereby, it is possible to design a system with a cycle number that is smaller than the total sum of the maximum access cycle numbers multiplied by the maximum access times over all requesters.
摘要翻译：提供了一种总线控制器，其包括处理装置，用于执行具有不同的循环数的电平的处理，这取决于请求者，所述请求者分别向公共存储器发出访问请求。当从当前循环次数预期超过限制循环数时，总线控制器以较小的循环次数选择执行处理的处理级别，或执行不对非实时总线的许可的控制访问请求。因此，可以设计一个周期数小于最大访问周期数乘以所有请求者的最大访问时间的总和的系统。

9. 发明授权

US06320906B1 Motion vector detecting circuit 失效
标题翻译：运动矢量检测电路
公开(公告)号：US06320906B1
公开(公告)日：2001-11-20
申请号：US08859428
申请日：1997-05-20
申请人： Masaki Toyokura , Takuya Jinbo
发明人： Masaki Toyokura , Takuya Jinbo
IPC分类号： H04N712
CPC分类号： H04N19/533 , H04N5/145 , H04N19/57
摘要： In an animation encoding process, a motion vector which can minimize an AC component included in a discrete cosine transform result is detected. For this purpose, a block X (i, j) to be processed is extracted from an input image X, and a prospective reference block Yk (i, J) is extracted from a reference image Y, wherein k is an integer depending upon the size of a motion vector search range, i=0, . . . , or 3, and j=0, . . . , or 63. From each pixel value in each sub block (including 8×8 pixels) of the block to be processed, an average value Xa (i) of pixels in the sub block is subtracted, and from each pixel value in each sub block (including 8×8 pixels) of the prospective reference block, an average value Yka (i) of pixels in the sub block is subtracted. Then, an evaluation value Sk for block matching is calculated. The prospective reference block having the minimum evaluation value is selected as a reference block among the plural prospective reference blocks, so as to obtain a motion vector V corresponding to the positional relationship between the block to be processed and the reference block.
摘要翻译：在动画编码处理中，检测出可以最小化包含在离散余弦变换结果中的AC分量的运动矢量。为此，从输入图像X提取要处理的块X（i，j），并从参考图像Y提取预期参考块Y k（i，j），其中k是取决于运动矢量搜索范围的大小，i = 0，。。。，或3，并且j = 0。。。或63.根据要处理的块的每个子块（包括8×8像素）中的每个像素值，减去子块中的像素的平均值Xa（i），并且从每个子块中的每个像素值（包括8×8像素），减去子块中的像素的平均值Yka（i）。然后，计算块匹配的评价值Sk。在多个预期参考块中选择具有最小评估值的预期参考块作为参考块，以获得与待处理块和参考块之间的位置关系相对应的运动矢量V.

10. 发明授权

US5583803A Two-dimensional orthogonal transform processor 失效
标题翻译：二维正交变换处理器
公开(公告)号：US5583803A
公开(公告)日：1996-12-10
申请号：US364116
申请日：1994-12-27
申请人： Yoshifumi Matsumoto , Masaki Toyokura
发明人： Yoshifumi Matsumoto , Masaki Toyokura
IPC分类号： G06F17/14 , G06F7/38
CPC分类号： G06F17/147
摘要： The two-dimensional DCT (discrete cosine transform) of plural n.times.n data items is carried out at high speed, with requiring less hardware. X(h) is an operation in which row vectors of A(h) are sequentially transmitted from a first memory to a one-dimensional DCT processor for product-of-matrices computations and the products thus found are sequentially written to at addresses of corresponding row vectors of B(h) of a second memory. Y(h) is an operation in which column vectors of B(h) are sequentially transmitted from the second memory to the one-dimensional DCT processor for product-of-matrices computations and the products thus found are sequentially written to at addresses of corresponding column vectors of C(h) of the first memory. The operation X(h) starts at h=1 and ends at h=m. Then, the operation Y(h) starts at h=1 and ends at h=m. The one-dimensional DCT processor performs the pipelining operation of n-element one-dimensional vectors for product-of-matrices computations.
摘要翻译：多个nxn数据项的二维DCT（离散余弦变换）以较高的速度执行，需要较少的硬件。 X（h）是对于矩阵的乘积运算，从第一存储器向一维DCT处理器依次发送A（h）的行向量的操作，并且将如此找到的乘积顺序地写入对应的地址第二存储器的B（h）的行向量。 Y（h）是从第二存储器向一维DCT处理器顺序发送B（h）的列向量到矩阵计算的操作，并且将如此找到的乘积顺序写入到相应的地址第一存储器的C（h）的列向量。操作X（h）从h = 1开始，以h = m结束。然后，操作Y（h）从h = 1开始，以h = m结束。一维DCT处理器执行用于矩阵计算的n元素一维向量的流水线操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式