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    • 4. 发明授权
    • Variable-length decoding apparatus
    • 可变长度解码装置
    • US5604499A
    • 1997-02-18
    • US358597
    • 1994-12-14
    • Eiji MiyagoshiHiroshi ImanishiHiroshi Takeno
    • Eiji MiyagoshiHiroshi ImanishiHiroshi Takeno
    • H03M7/42H03M7/40
    • H03M7/425
    • A prefix data generating portion is arranged such that a bit string having bits in predetermined number supplied from a barrel shifter is compared, from the head part thereof, with predetermined patterns and that there is supplied a less-bit bank address assigned to the identical predetermined pattern. In a look-up table, a decoded data is addressed using (i) an upper address of the bank address and (ii) a lower address of a plurality of remaining bits of the code, other than the predetermined pattern. Accordingly, the look-up table can be addressed with an address in which the number of bits is smaller than that of the code. This reduces the look-up table in capacity, enabling to provide a variable-length decoding apparatus reduced in hardware size.
    • 前缀数据产生部分被布置成使得从其头部分将具有预定数量的从桶形移位器提供的位的比特串与预定模式进行比较,并且提供分配给相同预定的 模式。 在查找表中,使用(i)存储体地址的高地址和(ii)除了预定模式之外的代码的多个剩余位的较低地址来寻址解码数据。 因此,查找表可以用比特数小于代码的地址来寻址。 这减少了查找表的容量,使得能够提供减少硬件尺寸的可变长度解码装置。
    • 5. 发明授权
    • Microcontroller, data processing system and task switching control method
    • 微控制器,数据处理系统和任务切换控制方法
    • US06243735B1
    • 2001-06-05
    • US09144474
    • 1998-08-31
    • Hiroshi ImanishiToshiyuki Araki
    • Hiroshi ImanishiToshiyuki Araki
    • G06F900
    • G06F9/4881G06F9/3009G06F9/3851G06F9/463
    • A processor, a task management table, and a scheduler are built in a microcontroller. The processor sequentially runs a plurality of tasks for controlling hardware engines (cores) respectively allocated thereto. The task management table stores task management information which includes state information (ST INFO) representative of the execution state of each task, priority information (PRI INFO) representative of the execution priority of each task, and core identification information (CID INFO) representative of the allocation of the tasks to the cores. The scheduler allows the processor to switch between tasks on the basis of the task management information when a given instruction is decoded or when the execution of any one of the cores is terminated.
    • 处理器,任务管理表和调度器内置在微控制器中。 处理器顺序地运行用于控制分配给其的硬件引擎(内核)的多个任务。 任务管理表存储表示各任务的执行状态的状态信息(ST INFO)的任务管理信息,表示各任务的执行优先级的优先级信息(PRI INFO)以及代表每个任务的执行优先级的核心识别信息(CID INFO) 将任务分配给内核。 调度器允许处理器在给定指令被解码时或当任一核心的执行终止时基于任务管理信息在任务之间切换。
    • 9. 发明授权
    • Code converter, variable length code decoder, and associated methods
    • 代码转换器,可变长度码解码器和相关方法
    • US5870039A
    • 1999-02-09
    • US877241
    • 1997-06-17
    • Hiroshi ImanishiMasaki Toyokura
    • Hiroshi ImanishiMasaki Toyokura
    • G11B20/10H03M7/30H03M7/40
    • G11B20/10H03M7/30H03M7/40
    • The present invention makes it possible to achieve restoration of decoding processing more intricately in comparison with commonly-used techniques. The present invention increases post-restoration data reliability and is applicable to real-time decoding processing. A variable length code converter of the present invention provides an abnormal code detection signal when a bit-string subjected to conversion corresponds to none of variable length codes that belong in predetermined coding systems. At this time, a controller provides an error signal, and according to the error signal a bit-string is continuously output from a memory which stores bit-strings to be decoded. When the controller detects a header indicative of data partition from an output bit-string of the memory, it cancels the error signal. As a result, bit-string decoding resumes after the detected header.
    • 与普通技术相比,本发明可以更复杂地实现解码处理的恢复。 本发明提高了恢复后数据的可靠性,并且适用于实时解码处理。 本发明的可变长度码转换器当经过转换的位串对应于不属于预定编码系统的可变长度码时,提供异常码检测信号。 此时,控制器提供误差信号,并且根据误差信号,从存储要解码的位串的存储器连续输出位串。 当控制器从存储器的输出位串检测到指示数据分区的头部时,它消除误差信号。 结果,在检测到的报头之后,重新开始位串解码。
    • 10. 发明授权
    • Apparatus and method for decoding variable-length code
    • 用于解码可变长度码的装置和方法
    • US5625355A
    • 1997-04-29
    • US379900
    • 1995-01-27
    • Hiroshi TakenoEiji MiyagoshiHiroshi ImanishiShintarou NakataniToshihide Akiyama
    • Hiroshi TakenoEiji MiyagoshiHiroshi ImanishiShintarou NakataniToshihide Akiyama
    • H03M7/42H03M7/40
    • H03M7/425
    • A variable-length-code decoder of this invention decodes an input bit stream including an input bit string having a codeword of a fixed-length code and a plurality of codewords of variable-length codes combined in a predetermined format. The decoder includes: a shifter for shifting the input bit string by a desired number of bits; a pattern detector for detecting a specific pattern in the bit string, and outputting a detection signal; two code tables provided for the respective variable-length codes, each code table having the length of each codeword (codeword length) and the decoded-word corresponding to the codeword, and outputting a codeword length and a decoded-word of a corresponding codeword based on the bit string output from the shifter; a processor for storing the format of the input bit string, outputting the length of the fixed-length code and decoded data of the fixed-length code, and selecting, for each of the variable-length codewords, one of the code tables to which the variable-length codeword belongs, based on the detection signal and the format; a codelength selector for selecting the codeword length or the fixed-length code, and for setting the shift amount for the input bit string in the shifter; and an output circuit for selectively outputting the decoded-word or the decoded data.
    • 本发明的可变长度码解码器对输入比特流解码,该输入比特流包括具有固定长度码的码字的输入比特串和以预定格式组合的可变长度码的多个码字。 解码器包括:移位器,用于将输入位串移位所需位数; 用于检测比特串中的特定模式的模式检测器,并输出检测信号; 为每个可变长度码提供两个码表,每个码表具有每个码字的长度(码字长度)和与码字对应的解码字,并输出码字长度和相应码字的解码字 来自移位器的位串输出; 用于存储输入位串的格式的处理器,输出固定长度代码的长度和固定长度代码的解码数据,并且对于每个可变长度代码字,选择一个代码表, 可变长度码字基于检测信号和格式属于; 用于选择码字长度或固定长度码的码长选择器,以及用于设置移位器中输入比特串的移位量; 以及用于选择性地输出解码字或解码数据的输出电路。