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    • 9. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08390046B2
    • 2013-03-05
    • US12947254
    • 2010-11-16
    • Jun KawaharaYoshihiro HayashiIppei Kume
    • Jun KawaharaYoshihiro HayashiIppei Kume
    • H01L29/772
    • H01L23/53238H01L27/0207H01L27/10814H01L27/10852H01L27/10855H01L27/10882H01L27/10894H01L28/91H01L2924/0002H01L2924/00
    • A semiconductor device of the present invention has a semiconductor substrate having a transistor formed thereon; a multi-layered interconnect formed on the semiconductor substrate, and having a plurality of interconnect layers, respectively composed of an interconnect and an insulating film, stacked therein; and a capacitance element having a lower electrode (lower electrode film), a capacitor insulating film, and an upper electrode (upper electrode film), all of which being embedded in the multi-layered interconnect, so as to compose a memory element, and further includes at least one layer of damascene-structured copper interconnect (second-layer interconnect) formed between the capacitance element and the transistor; the upper surface of one of the interconnects (second-layer interconnect) and the lower surface of the capacitance element are aligned nearly in the same plane; and at least one layer of copper interconnect (plate line interconnect) is formed over the capacitance element.
    • 本发明的半导体器件具有形成在其上的晶体管的半导体衬底; 形成在半导体衬底上的多层互连,并且具有分别由互连和绝缘膜组成的多个互连层,堆叠在其中; 以及具有下部电极(下部电极膜),电容器绝缘膜和上部电极(上部电极膜)的电容元件,其全部嵌入在多层互连件中,以构成存储元件,以及 还包括形成在电容元件和晶体管之间的至少一层镶嵌结构的铜互连(第二层互连); 一个互连(第二层互连)和电容元件的下表面的上表面几乎在同一平面内排列; 并且在电容元件上形成至少一层铜互连(板线互连)。
    • 10. 发明申请
    • SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
    • 半导体器件及其制造方法
    • US20090309186A1
    • 2009-12-17
    • US12519706
    • 2007-12-25
    • Naoya InoueIppei KumeJun KawaharaYoshihiro Hayashi
    • Naoya InoueIppei KumeJun KawaharaYoshihiro Hayashi
    • H01L27/06H01L21/02
    • H01L23/5228H01L23/5223H01L23/53238H01L27/0688H01L2924/0002H01L2924/3011H01L2924/00
    • A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.
    • 通过在同一步骤中制造包括下电极,电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。 由于电容器元件的下电极衬有下层布线层(Cu布线),所以下电极具有极低的电阻。 因此,即使下电极的膜厚变薄,寄生电阻也不会增加。 电阻元件形成为具有与电容器元件的下电极相同的膜厚度。 由于下部电极的膜厚薄,所以作为具有高电阻的电阻器。 在无源元件的顶层中,设置无源元件帽绝缘膜,当蚀刻电容器元件的上电极的接触时,其被用作蚀刻停止层。