专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08250548B2 Method for controlling heterogeneous multiprocessor and multigrain parallelizing compiler 有权
标题翻译：用于控制异构多处理器和多线并行编译器的方法
公开(公告)号：US08250548B2
公开(公告)日：2012-08-21
申请号：US11656531
申请日：2007-01-23
申请人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Yasutaka Wada , Masaki Ito , Hiroaki Shikano
发明人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Yasutaka Wada , Masaki Ito , Hiroaki Shikano
IPC分类号： G06F9/45
CPC分类号： G06F9/5044 , G06F2209/5012 , Y02D10/22
摘要： A heterogeneous multiprocessor system including a plurality of processor elements having mutually different instruction sets and structures avoids a specific processor element from being short of resources to improve throughput. An executable task is extracted based on a preset depending relationship between a plurality of tasks, and the plurality of first processors are allocated to a general-purpose processor group based on a depending relationship among the extracted tasks. A second processor is allocated to an accelerator group, a task to be allocated is determined from the extracted tasks based on a priority value for each of tasks, and an execution cost of executing the determined task by the first processor is compared with an execution cost of executing the task by the second processor. The task is allocated to one of the general-purpose processor group and the accelerator group that is judged to be lower as a result of the cost comparison.
摘要翻译：包括具有相互不同的指令集和结构的多个处理器元件的异构多处理器系统避免了特定的处理器元件缺少资源以提高吞吐量。基于多个任务之间的预设依赖关系来提取可执行任务，并且基于提取的任务之间的依赖关系将多个第一处理器分配给通用处理器组。将第二处理器分配给加速器组，基于每个任务的优先级值从所提取的任务确定要分配的任务，并且将由第一处理器执行所确定的任务的执行成本与执行成本进行比较由第二处理器执行任务。该任务被分配给作为成本比较的结果被判断为较低的通用处理器组和加速器组中的一个。

2. 发明申请

US20100146310A1 Multiprocessor system and multigrain parallelizing compiler 有权
标题翻译：多处理器系统和多线并行编译器
公开(公告)号：US20100146310A1
公开(公告)日：2010-06-10
申请号：US12654956
申请日：2010-01-11
申请人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Masaki Ito , Hiroaki Shikano
发明人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Masaki Ito , Hiroaki Shikano
IPC分类号： G06F1/26 , G06F1/04
CPC分类号： G06F9/5044 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F8/456 , G06F9/30083 , G06F9/4893 , G06F9/5094 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24
摘要： Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.
摘要翻译：提供了一种在系统中使用的多处理器系统和编译器，用于从要处理的输入程序自动提取具有并行性的任务，通过根据处理器单元的特性布置任务来执行调度以有效地操作处理器单元，并且生成用于优化的代码通过估计处理器单元的处理量来确定系统频率和电源电压。

3. 发明授权

US07895453B2 Multiprocessor system and multigrain parallelizing compiler 有权
标题翻译：多处理器系统和多线并行编译器
公开(公告)号：US07895453B2
公开(公告)日：2011-02-22
申请号：US11660104
申请日：2006-04-12
申请人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Masaki Ito , Hiroaki Shikano
发明人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Masaki Ito , Hiroaki Shikano
IPC分类号： G06F1/00
CPC分类号： G06F9/5044 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F8/456 , G06F9/30083 , G06F9/4893 , G06F9/5094 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24
摘要： Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.
摘要翻译：提供了一种在系统中使用的多处理器系统和编译器，用于从要处理的输入程序自动提取具有并行性的任务，通过根据处理器单元的特性布置任务来执行调度以有效地操作处理器单元，并且生成用于优化的代码通过估计处理器单元的处理量来确定系统频率和电源电压。

4. 发明申请

US20070283358A1 Method for controlling heterogeneous multiprocessor and multigrain parallelizing compiler 有权
标题翻译：用于控制异构多处理器和多线并行编译器的方法
公开(公告)号：US20070283358A1
公开(公告)日：2007-12-06
申请号：US11656531
申请日：2007-01-23
申请人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Yasutaka Wada , Masaki Ito , Hiroaki Shikano
发明人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Yasutaka Wada , Masaki Ito , Hiroaki Shikano
IPC分类号： G06F9/50
CPC分类号： G06F9/5044 , G06F2209/5012 , Y02D10/22
摘要： A heterogeneous multiprocessor system including a plurality of processor elements having mutually different instruction sets and structures avoids a specific processor element from being short of resources to improve throughput. An executable task is extracted based on a preset depending relationship between a plurality of tasks, and the plurality of first processors are allocated to a general-purpose processor group based on a depending relationship among the extracted tasks. A second processor is allocated to an accelerator group, a task to be allocated is determined from the extracted tasks based on a priority value for each of tasks, and an execution cost of executing the determined task by the first processor is compared with an execution cost of executing the task by the second processor. The task is allocated to one of the general-purpose processor group and the accelerator group that is judged to be lower as a result of the cost comparison.
摘要翻译：包括具有相互不同的指令集和结构的多个处理器元件的异构多处理器系统避免了特定的处理器元件缺少资源以提高吞吐量。基于多个任务之间的预设依赖关系来提取可执行任务，并且基于提取的任务之间的依赖关系将多个第一处理器分配给通用处理器组。将第二处理器分配给加速器组，基于每个任务的优先级值从所提取的任务确定要分配的任务，并且将由第一处理器执行所确定的任务的执行成本与执行成本进行比较由第二处理器执行任务。该任务被分配给作为成本比较的结果被判断为较低的通用处理器组和加速器组中的一个。

5. 发明申请

US20070255929A1 Multiprocessor System and Multigrain Parallelizing Compiler 有权
标题翻译：多处理器系统和多串并行编译器
公开(公告)号：US20070255929A1
公开(公告)日：2007-11-01
申请号：US11660104
申请日：2006-04-12
申请人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Masaki Ito , Hiroaki Shikano
发明人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Masaki Ito , Hiroaki Shikano
IPC分类号： G06F9/00
CPC分类号： G06F9/5044 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F8/456 , G06F9/30083 , G06F9/4893 , G06F9/5094 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24
摘要： Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.
摘要翻译：提供了一种在系统中使用的多处理器系统和编译器，用于从要处理的输入程序自动提取具有并行性的任务，通过根据处理器单元的特性布置任务来执行调度以有效地操作处理器单元，并且生成用于优化的代码通过估计处理器单元的处理量来确定系统频率和电源电压。

6. 发明授权

US08812880B2 Multiprocessor system and multigrain parallelizing compiler 有权
标题翻译：多处理器系统和多线并行编译器
公开(公告)号：US08812880B2
公开(公告)日：2014-08-19
申请号：US12654956
申请日：2010-01-11
申请人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Masaki Ito , Hiroaki Shikano
发明人： Hironori Kasahara , Keiji Kimura , Jun Shirako , Masaki Ito , Hiroaki Shikano
IPC分类号： G06F1/00 , G06F9/50 , G06F1/32 , G06F9/45 , G06F9/48
CPC分类号： G06F9/5044 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F8/456 , G06F9/30083 , G06F9/4893 , G06F9/5094 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24
摘要： Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.
摘要翻译：提供了一种在系统中使用的多处理器系统和编译器，用于从要处理的输入程序自动提取具有并行性的任务，通过根据处理器单元的特性布置任务来执行调度以有效地操作处理器单元，并且生成用于优化的代码通过估计处理器单元的处理量来确定系统频率和电源电压。

7. 发明授权

US08051412B2 Global compiler for controlling heterogeneous multiprocessor 有权
标题翻译：用于控制异构多处理器的全局编译器
公开(公告)号：US08051412B2
公开(公告)日：2011-11-01
申请号：US11716563
申请日：2007-03-12
申请人： Hironori Kasahara , Keiji Kimura , Hiroaki Shikano
发明人： Hironori Kasahara , Keiji Kimura , Hiroaki Shikano
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： Performance of a heterogeneous multiprocessor is reduced as much as possible within a short time without any awareness of parallelization matched with a configuration of the heterogeneous multiprocessor. In a heterogeneous multiprocessor system, tasks having parallelism are automatically extracted by a compiler, a portion to be efficiently processed by a dedicated processor is extracted from an input program being a processing target, and processing time is estimated. Thus, by arranging the tasks according to PU characteristics, scheduling for efficiently operating a plurality of PU's in parallel is carried out.
摘要翻译：异构多处理器的性能在短时间内尽可能地减少，而并不意识到并行化与异构多处理器的配置相匹配。在异构多处理器系统中，由编译器自动提取具有并行性的任务，从作为处理目标的输入程序提取要由专用处理器高效处理的部分，并且估计处理时间。因此，通过根据PU特性布置任务，执行并行地高效地操作多个PU的调度。

8. 发明申请

US20070283337A1 Global compiler for controlling heterogeneous multiprocessor 有权
标题翻译：用于控制异构多处理器的全局编译器
公开(公告)号：US20070283337A1
公开(公告)日：2007-12-06
申请号：US11716563
申请日：2007-03-12
申请人： Hironori Kasahara , Keiji Kimura , Hiroaki Shikano
发明人： Hironori Kasahara , Keiji Kimura , Hiroaki Shikano
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： Performance of a heterogeneous multiprocessor is educed as much as possible within a short time without any awareness of parallelization matched with a configuration of the heterogeneous multiprocessor. In a heterogeneous multiprocessor system, tasks having parallelism are automatically extracted by a compiler, a portion to be efficiently processed by a dedicated processor is extracted from an input program being a processing target, and processing time is estimated. Thus, by arranging the tasks according to PU characteristics, scheduling for efficiently operating a plurality of PU's in parallel is carried out.
摘要翻译：在短时间内尽可能地提供异构多处理器的性能，而并不意识到并行化与异构多处理器的配置相匹配。在异构多处理器系统中，由编译器自动提取具有并行性的任务，从作为处理目标的输入程序中提取要由专用处理器高效处理的部分，并且估计处理时间。因此，通过根据PU特性布置任务，执行并行地高效地操作多个PU的调度。

9. 发明授权

US08200934B2 Data transfer unit in multi-core processor 有权
标题翻译：数据传输单元在多核处理器中
公开(公告)号：US08200934B2
公开(公告)日：2012-06-12
申请号：US11865669
申请日：2007-10-01
申请人： Hironori Kasahara , Keiji Kimura , Takashi Todaka , Tatsuya Kamei , Toshihiro Hattori
发明人： Hironori Kasahara , Keiji Kimura , Takashi Todaka , Tatsuya Kamei , Toshihiro Hattori
IPC分类号： G06F12/00
CPC分类号： G06F15/167
摘要： To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.
摘要翻译：为了减少处理器核心之间的数据传输的开销并提高处理器的处理能力，提供了一种处理器，包括：用于执行计算处理的CPU; 用于存储数据的内部存储器; 以及数据传送单元，用于在内部存储器和共享存储器之间执行数据传送，其中：数据传送单元包括：命令链模块，用于执行由包括数据传送指令的多个命令形成的命令序列; 以及监视器模块，用于读取预先在内部存储器中设置的数据并重复监视数据，直到数据的比较值和值变得彼此相等时，当这样读取的命令序列的多个命令之一是预定命令命令链模块在监控模块完成监控后，在命令序列中执行下一个命令。

10. 发明申请

US20100174876A1 MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATION METHOD, AND PROGRAM 有权
标题翻译：内存管理方法，信息处理设备，程序创建方法和程序
公开(公告)号：US20100174876A1
公开(公告)日：2010-07-08
申请号：US12525404
申请日：2008-02-27
申请人： Hironori Kasahara , Keiji Kimura , Hirofumi Nakano , Takumi Nito , Takanori Maruyama , Tsuyoshi Miura , Tomohiro Tagawa
发明人： Hironori Kasahara , Keiji Kimura , Hirofumi Nakano , Takumi Nito , Takanori Maruyama , Tsuyoshi Miura , Tomohiro Tagawa
IPC分类号： G06F12/00 , G06F9/312 , G06F12/06
CPC分类号： G06F9/5033 , G06F8/453 , G06F9/4881 , G06F9/5016 , G06F12/0284 , G06F12/0646 , G06F2209/483 , G06F2209/5017
摘要： Provided is a method for managing a memory storage region used by a processor. The processor is connected to the memory that stores data accessed while a task is being executed. The memory management method including the steps of: dividing the memory area of the memory into blocks having a plurality of different sizes; selecting a block having a size matching a size of the data accessed while the task is being executed; and storing the data accessed while the task is being executed in the selected block.
摘要翻译：提供了一种用于管理由处理器使用的存储器存储区域的方法。处理器连接到存储器，用于存储在执行任务时访问的数据。存储器管理方法包括以下步骤：将存储器的存储区域划分为具有多个不同大小的块; 选择具有与执行任务期间访问的数据大小匹配的大小的块; 并且在所选择的块中存储在执行任务期间访问的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式