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1. 发明授权

US08521920B2 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US08521920B2
公开(公告)日：2013-08-27
申请号：US12844071
申请日：2010-07-27
申请人： Takumi Nito , Masashi Takada , Tetsuya Yamada
发明人： Takumi Nito , Masashi Takada , Tetsuya Yamada
IPC分类号： G06F13/28
CPC分类号： G06F12/1081 , G06F12/145
摘要： The data processor with access protection which has higher reliability during data transfer control according to a transfer condition set by a CPU. The data processor has: a CPU; a memory management section operable to control data transfer by the CPU; and a transfer controller operable to control the data transfer. The transfer controller holds identification information which the memory management section uses for access protection. When producing an address for transfer according to the setting of the CPU, the transfer controller starts data transfer on the condition that the identification information corresponding to the address for transfer matches the identification information of the CPU at the setting of a transfer condition, etc.
摘要翻译：具有访问保护的数据处理器，根据CPU设置的传送条件，在数据传输控制期间具有更高的可靠性。数据处理器有：一个CPU; 存储器管理部分，用于控制CPU的数据传输; 以及可操作以控制数据传送的传送控制器。传输控制器保存存储器管理部分用于访问保护的识别信息。当根据CPU的设置生成用于传送的地址时，转移控制器在转移条件设置等的情况下，在与传送地址相对应的识别信息与CPU的识别信息相匹配的条件下开始数据传送。

2. 发明申请

US20100174876A1 MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATION METHOD, AND PROGRAM 有权
标题翻译：内存管理方法，信息处理设备，程序创建方法和程序
公开(公告)号：US20100174876A1
公开(公告)日：2010-07-08
申请号：US12525404
申请日：2008-02-27
申请人： Hironori Kasahara , Keiji Kimura , Hirofumi Nakano , Takumi Nito , Takanori Maruyama , Tsuyoshi Miura , Tomohiro Tagawa
发明人： Hironori Kasahara , Keiji Kimura , Hirofumi Nakano , Takumi Nito , Takanori Maruyama , Tsuyoshi Miura , Tomohiro Tagawa
IPC分类号： G06F12/00 , G06F9/312 , G06F12/06
CPC分类号： G06F9/5033 , G06F8/453 , G06F9/4881 , G06F9/5016 , G06F12/0284 , G06F12/0646 , G06F2209/483 , G06F2209/5017
摘要： Provided is a method for managing a memory storage region used by a processor. The processor is connected to the memory that stores data accessed while a task is being executed. The memory management method including the steps of: dividing the memory area of the memory into blocks having a plurality of different sizes; selecting a block having a size matching a size of the data accessed while the task is being executed; and storing the data accessed while the task is being executed in the selected block.
摘要翻译：提供了一种用于管理由处理器使用的存储器存储区域的方法。处理器连接到存储器，用于存储在执行任务时访问的数据。存储器管理方法包括以下步骤：将存储器的存储区域划分为具有多个不同大小的块; 选择具有与执行任务期间访问的数据大小匹配的大小的块; 并且在所选择的块中存储在执行任务期间访问的数据。

3. 发明申请

US20110055435A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20110055435A1
公开(公告)日：2011-03-03
申请号：US12844071
申请日：2010-07-27
申请人： Takumi NITO , Masashi TAKADA , Tetsuya YAMADA
发明人： Takumi NITO , Masashi TAKADA , Tetsuya YAMADA
IPC分类号： G06F13/28 , G06F12/10
CPC分类号： G06F12/1081 , G06F12/145
摘要： The data processor provides an access protection with higher reliability during data transfer control according to a transfer condition set by CPU. The data processor has: CPU; a memory management section operable to control data transfer by CPU; and a transfer controller operable to control data transfer. The transfer controller holds identification information which the memory management section uses for access protection. When producing an address for transfer according to the setting of CPU, the transfer controller starts data transfer on condition that the identification information corresponding to the address for transfer matches the identification information of CPU at the setting of a transfer condition, etc.
摘要翻译：根据CPU设置的传输条件，数据处理器在数据传输控制期间提供更高可靠性的访问保护。数据处理器有：CPU; 存储器管理部分，用于控制CPU的数据传输; 以及可操作以控制数据传送的传送控制器。传输控制器保存存储器管理部分用于访问保护的识别信息。当根据CPU的设置生成用于传送的地址时，传送控制器开始数据传送，条件是在传送条件设置等情况下，与传送地址相对应的识别信息与CPU的识别信息相匹配。

4. 发明申请

US20100082940A1 INFORMATION PROCESSOR 审中-公开
标题翻译：信息处理器
公开(公告)号：US20100082940A1
公开(公告)日：2010-04-01
申请号：US12546748
申请日：2009-08-25
申请人： TAKUMI NITO , Masashi TAKADA
发明人： TAKUMI NITO , Masashi TAKADA
IPC分类号： G06F15/76 , G06F12/08 , G06F9/02
CPC分类号： G06F12/1466 , G06F12/084
摘要： An information processor controls accesses to a cache memory from application software programs differing in range of addresses, accesses to which are authorized. The cache memory blocks an access to an unauthorized address. In the information processor, an ID is assigned to each application software program, and the tag field of the cache memory is extended. Further, in performing “Cache Fill” (i.e. reading main memory data into the cache memory), the ID is recorded. At the time of making a cache hit judgment, the access control is performed by comparing the extended tag field with ID of an application software program group of an access requester.
摘要翻译：信息处理器控制对地址范围不同的应用软件程序对高速缓冲存储器的访问，访问权限被授权。高速缓冲存储器阻止访问未经授权的地址。在信息处理器中，将ID分配给每个应用软件程序，并且缓存存储器的标签字段被扩展。此外，在执行“缓存填充”（即将主存储器数据读入高速缓存存储器）时，记录该ID。在进行缓存命中判断时，通过将扩展标签字段与访问请求者的应用软件程序组的ID进行比较来执行访问控制。

5. 发明申请

US20150149705A1 INFORMATION-PROCESSING SYSTEM 审中-公开
标题翻译：信息处理系统
公开(公告)号：US20150149705A1
公开(公告)日：2015-05-28
申请号：US14403815
申请日：2012-05-25
申请人： Takumi Nito
发明人： Takumi Nito
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0616 , G06F3/0635 , G06F3/0659 , G06F3/0688
摘要： Information-processing system including a first information-processing unit, and a second information-processing unit, when the concept of wear leveling is applied to distribution of workloads to the respective information-processing units, the lives of the nonvolatile memories of the first information-processing unit and the second information-processing unit come to ends at almost exactly the same time, comprising a first counter that counts a number of times of writing in the first memory device, and a second counter that counts a number of times of writing in the second memory device, and assignment of workloads to the first information-processing unit and the second information-processing unit is performed based on a replacement time of the first memory device, a replacement time of the second memory device, output of the first counter, and output of the second counter. Thereby, the above described problem is solved.
摘要翻译：信息处理系统，包括第一信息处理单元和第二信息处理单元，当将磨损均衡的概念应用于各个信息处理单元的工作量分配时，第一信息的非易失性存储器的寿命处理单元和第二信息处理单元几乎完全相同地结束，包括对第一存储器件中的写入次数进行计数的第一计数器和对写入次数进行计数的第二计数器在第二存储装置中，基于第一存储装置的更换时间，第二存储装置的更换时间，第一存储装置的更新时间，第一存储装置的更新时间，第一存储装置的更新时间，计数器和第二个计数器的输出。由此，解决了上述问题。

6. 发明授权

US08438359B2 Memory management method, information processing device, program creation method, and program 有权
标题翻译：内存管理方法，信息处理装置，程序创建方法和程序
公开(公告)号：US08438359B2
公开(公告)日：2013-05-07
申请号：US12525404
申请日：2008-02-27
申请人： Hironori Kasahara , Keiji Kimura , Hirofumi Nakano , Takumi Nito , Takanori Maruyama , Tsuyoshi Miura , Tomohiro Tagawa
发明人： Hironori Kasahara , Keiji Kimura , Hirofumi Nakano , Takumi Nito , Takanori Maruyama , Tsuyoshi Miura , Tomohiro Tagawa
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/5033 , G06F8/453 , G06F9/4881 , G06F9/5016 , G06F12/0284 , G06F12/0646 , G06F2209/483 , G06F2209/5017
摘要： Provided is a method for managing a memory storage region used by a processor. The processor is connected to the memory that stores data accessed while a task is being executed. The memory management method including the steps of: dividing the memory area of the memory into blocks having a plurality of different sizes; selecting a block having a size matching a size of the data accessed while the task is being executed; and storing the data accessed while the task is being executed in the selected block.
摘要翻译：提供了一种用于管理由处理器使用的存储器存储区域的方法。处理器连接到存储器，用于存储在执行任务时访问的数据。存储器管理方法包括以下步骤：将存储器的存储区域划分为具有多个不同大小的块; 选择具有与执行任务期间访问的数据大小匹配的大小的块; 并且在所选择的块中存储在执行任务期间访问的数据。

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