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1. 发明授权

US5708800A High speed microprocessor for processing and transferring N-bits of M-bit data 失效
标题翻译：用于处理和传送N位M位数据的高速微处理器
公开(公告)号：US5708800A
公开(公告)日：1998-01-13
申请号：US487170
申请日：1995-06-07
申请人： Hiroshi Tateishi , Hiroki Takahashi , Kazuo Nakamura
发明人： Hiroshi Tateishi , Hiroki Takahashi , Kazuo Nakamura
IPC分类号： G06F12/04 , G06F5/00 , G06F9/30 , G06F9/315 , G06F7/10
CPC分类号： G06F5/00
摘要： A microprocessor comprises a control section for receiving a transfer instruction and transferring N-bits of M-bit data stored at a transfer-source address in a first memory to a transfer-destination address in a second memory in response to a received transfer instruction. In this microprocessor, the transfer of N-bits is performed with the execution of a single transfer instruction. Hence, the memory area required for storing the transfer instructions is reduced, and the residual memory area can be used for other purposes, which improves the efficiency in the use of the memory. The control section stores in the first memory of the microprocessor all the interim results obtained during the execution of a transfer instruction and outputs only the final result to the external memory, reducing the number of machine cycles required for data transfer between the microprocessor and the memory, and further reducing the execution time for data transfer in the microprocessor.
摘要翻译：微处理器包括控制部分，用于响应于接收到的传送指令，接收传送指令并将存储在第一存储器中的传送源地址的N位的M位数据传送到第二存储器中的传送目的地地址。在该微处理器中，通过执行单个传送指令来执行N位的传送。因此，存储转移指令所需的存储区域减少，并且剩余存储区域可以用于其他目的，这提高了存储器的使用效率。控制部分在微处理器的第一存储器中存储在执行传送指令期间获得的所有中间结果，并且仅将最终结果输出到外部存储器，从而减少微处理器和存储器之间的数据传送所需的机器周期数并且进一步减少微处理器中的数据传输的执行时间。

2. 发明授权

US07167996B2 Micro controller unit 有权
标题翻译：微控制器单元
公开(公告)号：US07167996B2
公开(公告)日：2007-01-23
申请号：US10690574
申请日：2003-10-23
申请人： Hiroki Takahashi , Kazuo Nakamura
发明人： Hiroki Takahashi , Kazuo Nakamura
IPC分类号： G06F1/12
CPC分类号： G06F1/08 , G06F1/10 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： It is an object to increase a speed of a CPU operation irrespective of an operation speed of a peripheral circuit and to prevent an increase in power consumption from being thereby caused. A clock generating circuit (10) generates two clocks having phases which are equal to each other, that is, a CPU clock (CLKCPU) and a bus clock (CLKBUS). A BIU (bus interface unit) (51) controls a code bus based on the CPU clock (CLKCPU) and controls a peripheral bus based on the bus clock (CLKBUS). The clock generating circuit (10) switches a frequency of each of the CPU clock (CLKCPU) and the bus clock (CLKBUS) depending on an operation mode of an MCU. For example, a speed of the CPU clock (CLKCPU) is set to be higher than that of the bus clock (CLKBUS) in order to carry out a high-speed operation of a CPU. Also in that case, the phases of both clocks are equal to each other. Consequently, the code bus and the peripheral bus in the BIU (51) can easily be controlled.
摘要翻译：本发明的目的是提高CPU运行的速度，而与外围电路的运行速度无关，并且防止由此引起的功耗的增加。时钟发生电路（10）产生具有彼此相等的相位的两个时钟，即CPU时钟（CLK＆lt; CPU＆gt;）和总线时钟（CLK＆lt; BUS＆lt; ）。 BIU（总线接口单元）（51）基于CPU时钟（CLK ）来控制代码总线，并且基于总线时钟（CLK ）。时钟发生电路（10）根据MCU的工作模式切换CPU时钟（CLK CPU ）和总线时钟（CLK 。例如，CPU时钟的速度（CLK＆lt; CPU＆lt;＆gt;）被设定为高于总线时钟（CLK＆lt; BUS＆gt;）的速度， CPU的高速运行。同样在这种情况下，两个时钟的相位彼此相等。因此，可以容易地控制BIU（51）中的代码总线和外围总线。

3. 发明授权

US06345365B1 Semiconductor device with an external delay circuit that delays an internal clock 失效
标题翻译：具有延迟内部时钟的外部延迟电路的半导体器件
公开(公告)号：US06345365B1
公开(公告)日：2002-02-05
申请号：US09247508
申请日：1999-02-10
申请人： Hiroki Takahashi , Kazuo Nakamura
发明人： Hiroki Takahashi , Kazuo Nakamura
IPC分类号： G06F104
CPC分类号： G06F1/10
摘要： A CPU (1) outputs a data signal (DI) in synchronization with an internal clock signal (Iclk). A device (101), which is an integrated circuit, is connected with a delay circuit (10) which is placed outside the device (101). The delay circuit (10) delays the internal clock signal (Iclk) for a delay time shorter than one cycle thereof, and thereby supplies the delayed signal as a delay clock signal (Dclk) to the device (101). A data transfer control circuit (2) delays the data signal (DI) for the delay time of the delay clock signal (Dclk) according to the delay clock signal (Dclk) and a control signal (CS) outputted by the CPU (1), and outputs the delayed data signal as a data signal (DE) to an external device. Since the external device operates in accordance with a control signal (WR) outputted synchronously with the internal clock signal (Iclk), a hold time corresponding to the delay time can be ensured. Thus, an external device, which requires a long hold time, is connectable with the device (101).
摘要翻译： CPU（1）与内部时钟信号（Iclk）同步地输出数据信号（DI）。作为集成电路的装置（101）与放置在装置（101）外部的延迟电路（10）连接。延迟电路（10）延迟内部时钟信号（Iclk）的延迟时间短于其一个周期，从而将延迟的信号作为延迟时钟信号（Dclk）提供给设备（101）。数据传输控制电路（2）根据延迟时钟信号（Dclk）和CPU（1）输出的控制信号（CS）延迟延迟时间信号（Dclk）的延迟时间的数据信号（DI），并将延迟的数据信号作为数据信号（DE）输出到外部设备。由于外部设备根据与内部时钟信号（Iclk）同步输出的控制信号（WR）进行工作，因此可以确保与延迟时间对应的保持时间。因此，需要长的保持时间的外部设备可与设备（101）连接。

4. 发明授权

US08830144B2 Display panel and display device 有权
标题翻译：显示面板和显示设备
公开(公告)号：US08830144B2
公开(公告)日：2014-09-09
申请号：US12661248
申请日：2010-03-12
申请人： Kazuo Nakamura , Katsuhide Uchino , Nobutoshi Asai , Hiroshi Sagawa
发明人： Kazuo Nakamura , Katsuhide Uchino , Nobutoshi Asai , Hiroshi Sagawa
IPC分类号： G09G3/30 , H01L27/32 , H01L51/52
CPC分类号： H01L27/3269 , G09G3/20 , G09G3/3208 , G09G2300/0421 , H01L27/322 , H01L51/5284 , H01L2227/32
摘要： A display panel includes: a plurality of pixel circuits formed in a matrix on a substrate; an insulating layer covering the plurality of pixel circuits; a plurality of light emitting elements connected to the plurality of pixel circuits, and arranged in a matrix on the insulating layer; a filtering layer including a light transmitting section at least in a part of a region facing the light emitting element and a light shielding section formed in a same plane as the light transmitting section, and formed on an opposite side from the pixel circuit in relation to the light emitting element; a light reflecting section formed in a region facing the light shielding section, and between the light emitting element and the filtering layer; and a light receiving element formed in a region facing the light shielding section, and on the pixel circuit side in relation to the light emitting element.
摘要翻译：显示面板包括：在基板上以矩阵形成的多个像素电路; 覆盖所述多个像素电路的绝缘层; 连接到所述多个像素电路的多个发光元件，并且以矩阵形式布置在所述绝缘层上; 滤光层，其至少在面向发光元件的区域的一部分中具有透光部，以及形成在与透光部相同的平面中的遮光部，并且形成在与像素电路相反的一侧发光元件; 在与所述遮光部对置的区域中形成的光反射部以及所述发光元件与所述滤光层之间的光反射部; 以及形成在面对遮光部的区域中的光接收元件，并且在像素电路侧相对于发光元件形成。

5. 发明申请

US20130200848A1 BATTERY PACK, METHOD FOR CHARGING/DISCHARGING SAME, AND POWER CONSUMPTION DEVICE 审中-公开
标题翻译：电池组，充电/放电方法和消耗电力装置
公开(公告)号：US20130200848A1
公开(公告)日：2013-08-08
申请号：US13879580
申请日：2011-09-08
申请人： Atsushi Ozawa , Kazuo Nakamura , Shin Hotta , Kentaro Marutani , Shinichi Uesaka
发明人： Atsushi Ozawa , Kazuo Nakamura , Shin Hotta , Kentaro Marutani , Shinichi Uesaka
IPC分类号： H02J7/00
CPC分类号： H02J7/0029 , B60L11/1855 , B60L2200/26 , H01M10/441 , H02J7/0019 , H02J7/0024 , H02J7/045 , Y02T10/7005 , Y02T10/705
摘要： Provided is a method for charging/discharging a battery pack having an auxiliary charging/discharging device and a battery assembly in which a plurality of secondary battery cell parallel modules, each of which includes a plurality of fasecondary battery cells connected in parallel, are connected in series, the method including, when there is no abnormality in the secondary battery cells during charging/discharging, connecting the auxiliary charging/discharging device in parallel to any of the secondary battery cell parallel modules, and when there is an abnormality in any of the secondary battery cells during charging/discharging, releasing connection to the secondary battery cell at which the abnormality has arisen in the secondary battery cell parallel module including the secondary battery cell at which the abnormality has arisen, and connecting the auxiliary charging/discharging device in parallel to the secondary battery cell parallel module including the secondary battery cell at which the abnormality has arisen.
摘要翻译：本发明提供一种具有辅助充电/放电装置和电池组件的电池组的充电/放电方法，其中包括并联连接的多个第二电池单元的多个二次电池单元并联模块连接在该方法包括当在充电/放电期间二次电池单元中没有异常时，将辅助充电/放电装置与任何二次电池单元并联模块并联连接，并且当任何一个在充放电期间的二次电池单元，在包括产生异常的二次电池的二次电池单元并联模块中发生异常的二次电池单元的连接，并且并联连接辅助充电/放电装置涉及包括二次电池单元a的二次电池单元并联模块这产生了异常。

6. 发明授权

US08330682B2 Display apparatus, display control apparatus, and display control method as well as program 有权
标题翻译：显示装置，显示控制装置，显示控制方法以及程序
公开(公告)号：US08330682B2
公开(公告)日：2012-12-11
申请号：US12543558
申请日：2009-08-19
申请人： Kazuo Nakamura , Katsuhide Uchino
发明人： Kazuo Nakamura , Katsuhide Uchino
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G2320/0233 , G09G2320/0285 , G09G2320/041 , G09G2320/043 , G09G2320/0693
摘要： A display apparatus includes: a plurality of pixel circuits arrayed in a matrix fashion; a light emitting circuit provided to each pixel circuit and emitting light correspondingly to a drive current; and a detection circuit provided to a predetermined pixel circuit and outputting a signal according to a temperature that varies with luminance of the light emitting circuit.
摘要翻译：显示装置包括：以矩阵方式排列的多个像素电路; 提供给每个像素电路并且对应于驱动电流发光的发光电路; 以及检测电路，其被提供给预定的像素电路，并且根据随着发光电路的亮度而变化的温度输出信号。

7. 发明授权

US08237691B2 Display driver circuit and DAC of a display device with partially overlapping positive and negative voltage ranges and reduced transistor breakdown voltage 失效
标题翻译：显示器件的显示驱动电路和DAC具有部分重叠的正负电压范围和降低的晶体管击穿电压
公开(公告)号：US08237691B2
公开(公告)日：2012-08-07
申请号：US12167263
申请日：2008-07-03
申请人： Kazuo Nakamura
发明人： Kazuo Nakamura
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027
摘要： A display driver circuit of a display device includes: a first DA converter for converting a digital data to a gray-scale potential within a first potential range; and a second DA converter for converting a digital data to a gray-scale potential within a second potential range lower than the first potential range. The first DA converter includes a first transistor of a first conductivity type outputting a gray-scale potential not less than the common potential. The second DA converter includes: a second transistor of the first conductivity type outputting a gray-scale potential not less than the common potential; and a third transistor of a second conductivity type outputting a gray-scale potential not more than the common potential. A substrate potential applied to a back gate of the second transistor is lower than a substrate potential applied to a back gate of the first transistor.
摘要翻译：显示装置的显示驱动电路包括：第一DA转换器，用于将数字数据转换为第一电位范围内的灰度级电位; 以及第二DA转换器，用于在低于第一电位范围的第二电位范围内将数字数据转换为灰度级电位。第一DA转换器包括输出不小于公共电位的灰度电位的第一导电类型的第一晶体管。第二DA转换器包括：第一导电类型的第二晶体管输出不小于公共电位的灰度电位; 以及第二导电类型的第三晶体管，其输出不大于所述公共电位的灰度电势。施加到第二晶体管的背栅极的衬底电位低于施加到第一晶体管的背栅极的衬底电位。

8. 发明授权

US08223107B2 Data driver and display apparatus using the same including clock control circuit and shift register circuit 失效
标题翻译：数据驱动器和使用其的显示装置包括时钟控制电路和移位寄存器电路
公开(公告)号：US08223107B2
公开(公告)日：2012-07-17
申请号：US11987860
申请日：2007-12-05
申请人： Kazuo Nakamura
发明人： Kazuo Nakamura
IPC分类号： G09G3/36
CPC分类号： G11C19/28 , G11C19/00
摘要： A data driver circuit includes a clock control circuit configured to generate a shift clock signal in synchronization to a clock signal; a shift register circuit having flip-flops in cascade-connection and configured to shift a pulse signal in synchronization with the shift clock signal, and a control circuit configured to receive a display data in response to the shifted pulse signal from the shift register circuit and to drive data lines of a display section based on display data to display the display data on the display section. The flip-flops are grouped in units of N (N is an integer of 2 or more) flip-flops into M (M is an integer of 2 or more) partial shift registers, and the shift register circuit is reset in units of partial shift registers.
摘要翻译：数据驱动电路包括：时钟控制电路，被配置为与时钟信号同步地生成移位时钟信号; 移位寄存器电路，其具有级联连接的触发器并且被配置为与所述移位时钟信号同步地移位脉冲信号;以及控制电路，被配置为响应于来自所述移位寄存器电路的移位的脉冲信号而接收显示数据，以及基于显示数据驱动显示部分的数据线，以在显示部分上显示显示数据。触发器以N（N为2以上的整数）触发器为单位分组为M（M为2以上的整数）部分移位寄存器，移位寄存器电路以部分移位寄存器

9. 发明申请

US20100285387A1 SEGMENTED-IN-SERIES SOLID OXIDE FUEL CELL 审中-公开
标题翻译： SEGMENTED-IN-SERIES固体氧化物燃料电池
公开(公告)号：US20100285387A1
公开(公告)日：2010-11-11
申请号：US12735270
申请日：2008-12-24
申请人： Kenjiro Fujita , Kazuo Nakamura , Yoshio Matsuzaki , Makoto Koi
发明人： Kenjiro Fujita , Kazuo Nakamura , Yoshio Matsuzaki , Makoto Koi
IPC分类号： H01M8/24
CPC分类号： H01M8/1213 , H01M8/0204 , H01M8/1286 , H01M8/2425 , H01M8/2428
摘要： There is obtained a segmented-in-series solid oxide fuel cell provided with a current turnaround structure and containing a porous electrically insulating substrate having a fuel flow path extending from a fuel feed port to a fuel discharge port, provided therein, and a pair of the top and back surfaces, in parallel with the fuel flow path, together with a pair of side-faces of the porous electrically insulating substrate, in the transverse direction thereof, provided on the exterior thereof, wherein solid oxide fuel cells made up by sequentially stacking an interconnector adjacent to a fuel electrode layer, the fuel electrode layer, an electrolyte layer, and an air electrode layer, and an interconnector adjacent to the air electrode layer in that order so as to be in parallel with the fuel flow path are disposed at intervals on the pair of the top and back surfaces, respectively.
摘要翻译：获得具有电流翻转结构的分段式串联固体氧化物燃料电池，并且包含具有从设置在其中的燃料供给口延伸到燃料排出口的燃料流路的多孔电绝缘基板和一对与燃料流动路径平行的顶表面和后表面与多孔电绝缘基板的横向方向上的一对侧面一起设置在其外部，其中固体氧化物燃料电池依次构成布置与燃料电极层相邻的互连器，燃料电极层，电解质层和空气电极层以及与空气电极层相邻的与金属流路平行的顺序的互连器分别在一对顶表面和后表面上的间隔。

10. 发明授权

US07777739B2 Display apparatus, digital-to-analog conversion circuit and digital-to-analog conversion method 有权
标题翻译：显示装置，数/模转换电路和数 - 模转换方法
公开(公告)号：US07777739B2
公开(公告)日：2010-08-17
申请号：US11339552
申请日：2006-01-26
申请人： Takashi Nakamura , Hirotaka Hayashi , Hisao Fujiwara , Masao Karube , Kazuo Nakamura , Masakatsu Kitani
发明人： Takashi Nakamura , Hirotaka Hayashi , Hisao Fujiwara , Masao Karube , Kazuo Nakamura , Masakatsu Kitani
IPC分类号： G09G5/00
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2300/0408 , G09G2310/0248 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2320/0233 , G09G2330/02 , G09G2330/021 , H03M1/804
摘要： A signal line drive circuit according to the present invention has: a latch circuit which latches digital pixel data; a D/A converter which converts a latch output from the latch circuit into an analog video signal; an AMP which amplifies the analog video signal converted by the D/A converter; and a signal selection circuit which selects a signal line to which the analog video signal amplified by the AMP is supplied. The AMP has: an odd number of inverters which are cascade-connected; capacitor elements which are respectively connected between stages of the inverters and between an input terminal of the inverter on a first stage and an output terminal of the inverter on a last stage; a first power supply line which supplies a power supply voltage to the inverter on the first stage; and a second power supply line which supplies a power supply voltage to inverters other than the inverter on the first stage. The accuracy of the AMP can be improved by separating the power supply line for only the inverter on the first stage.
摘要翻译：根据本发明的信号线驱动电路具有锁存数字像素数据的锁存电路; D / A转换器，其将来自锁存电路的锁存器输出转换为模拟视频信号; 放大由D / A转换器转换的模拟视频信号的AMP; 以及信号选择电路，其选择供给由AMP放大的模拟视频信号的信号线。 AMP具有：奇数级逆变器级联; 电容器元件分别连接在反相器的级之间，在第一级的反相器的输入端和最后级的反相器的输出端之间; 在第一级上向逆变器供给电源电压的第一电源线; 以及第二电源线，其向第一级上的逆变器的逆变器供给电源电压。通过在第一级分离仅逆变器的电源线，可以提高AMP的精度。

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