专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4980748A Semiconductor device made with a trenching process 失效
标题翻译：半导体器件采用开沟工艺制成
公开(公告)号：US4980748A
公开(公告)日：1990-12-25
申请号：US361554
申请日：1989-06-05
申请人： Hiroki Hozumi , Minoru Nakamura , Hiroyuki Miwa , Akio Kayanuma
发明人： Hiroki Hozumi , Minoru Nakamura , Hiroyuki Miwa , Akio Kayanuma
IPC分类号： H01L29/73 , H01L21/331 , H01L21/763 , H01L23/485 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/763 , H01L23/485 , H01L2924/0002
摘要： In a semiconductor device having trench-shaped element isolating regions formed in a semiconductor body and also a conductive layer extending on each element isolating region and connected to an impurity diffusion region of the semiconductor body, there is formed an insulator layer region between an extension of the conductive layer and the element isolating region, and the insulator layer region is buried in the surface portion of the semiconductor body. In such construction, the insulation space between the conductive layer and the semiconductor body can be increased while the distance between the element isolating region and the impurity diffusion region can be shortened to consequently diminish the parasitic capacitance between the conductive layer and the semiconductor body, hence attaining a faster operation in the semiconductor device. When the present invention is applied to a bipolar transistor integrated circuit, a superfast operation is ensured due to the reduction of the base-to-collector capacitance.

2. 发明授权

US5163178A Semiconductor device having enhanced impurity concentration profile 失效
标题翻译：具有增强浓度浓度特性的半导体器件
公开(公告)号：US5163178A
公开(公告)日：1992-11-10
申请号：US634454
申请日：1990-12-27
申请人： Takayuki Gomi , Minoru Nakamura , Hiroaki Anmo , Norikazu Chuchi , Hiroyuki Miwa , Akio Kayanuma , Koji Kobayashi
发明人： Takayuki Gomi , Minoru Nakamura , Hiroaki Anmo , Norikazu Chuchi , Hiroyuki Miwa , Akio Kayanuma , Koji Kobayashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8224 , H01L27/06 , H01L29/08 , H01L29/732 , H01L29/735
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8224 , H01L29/735
摘要： A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.

3. 发明授权

US6159784A Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US6159784A
公开(公告)日：2000-12-12
申请号：US332038
申请日：1999-06-14
申请人： Hiroaki Ammo , Hiroyuki Miwa
发明人： Hiroaki Ammo , Hiroyuki Miwa
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L27/0635
摘要： A method of producing a semiconductor device by which the resistivities of the base, collector, and source/drain regions in a Bi-CMOS are decreased and the production step is simplified. A method of producing a semiconductor device comprising the steps of forming a gate electrode (the first semiconductor layer) on a substrate; forming an insulating film; forming a second semiconductor layer; leaving the second semiconductor layer and the insulating film on the bipolar part and removing them on the CMOS part to form sidewalls on the side faces of the gate electrode; forming source/drain regions; forming a Ti layer over the entire surface and forming silicide on the surfaces of the second semiconductor layer, the source/drain regions, and the gate electrode; and forming a base electrode by patterning the second semiconductor layer.
摘要翻译：制造半导体器件的方法，其中Bi-CMOS中的基极，集电极和源极/漏极区的电阻率降低，并且制造步骤简化。一种制造半导体器件的方法，包括以下步骤：在衬底上形成栅电极（第一半导体层）; 形成绝缘膜; 形成第二半导体层; 将第二半导体层和绝缘膜留在双极部上，并在CMOS部分上去除它们，以在栅电极的侧面上形成侧壁; 形成源/漏区; 在整个表面上形成Ti层，并在第二半导体层，源/漏区和栅电极的表面上形成硅化物; 以及通过图案化所述第二半导体层形成基极。

4. 发明授权

US06136634A Method of manufacturing semiconductor resistors 失效
标题翻译：制造半导体电阻的方法
公开(公告)号：US06136634A
公开(公告)日：2000-10-24
申请号：US86208
申请日：1998-05-28
申请人： Katsuyuki Kato , Hiroyuki Miwa , Hiroaki Ammo
发明人： Katsuyuki Kato , Hiroyuki Miwa , Hiroaki Ammo
IPC分类号： H01L21/02 , H01L21/84 , H01L27/08 , H01L27/12 , H01L21/8238 , H01L21/8222 , H01L29/00 , H01L29/76
CPC分类号： H01L28/20 , H01L21/84 , H01L27/0802 , H01L27/1203
摘要： A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.
摘要翻译：即使在具有足够低的期望电阻值的微小尺寸的情况下也具有稳定的电阻值的高电阻多晶Si电阻器，其中在位于Si衬底上的绝缘膜上形成多晶Si膜，高对整个表面施加电阻制造离子注入，并且将中等电阻制造离子注入选择性地施加到多晶Si膜的中阻制造区域。选择性地将低电阻制造离子注入施加到多晶Si膜的低电阻制造区域。将产物退火以通过固相生长生长多晶Si膜，该膜被图案化以形成高电阻多晶硅电阻器，中等电阻多晶Si电阻器和低电阻多晶Si电阻器。

5. 发明授权

US5686032A Process of forming a gasket directly on workpiece, using a mold clamped to the workpiece 失效
标题翻译：使用夹在工件上的模具直接在工件上形成垫圈的过程
公开(公告)号：US5686032A
公开(公告)日：1997-11-11
申请号：US340414
申请日：1994-11-15
申请人： Tatsuya Mizobe , Masayuki Sumiyoshi , Hiroyuki Miwa
发明人： Tatsuya Mizobe , Masayuki Sumiyoshi , Hiroyuki Miwa
IPC分类号： F16J15/00 , B29C45/14 , B29C45/26 , B29C45/34 , B29C45/76 , B29C45/77 , B29C45/84 , C09K3/10 , F16J15/10 , F16J15/14 , B29C33/24
CPC分类号： B29C45/14336 , B29C45/2608 , B29C45/34 , B29C45/768 , B29C45/77 , F16J15/108 , B29C2045/14459 , B29C2945/76006 , B29C2945/76076 , B29C2945/76307 , B29C2945/76381 , B29C2945/76498 , B29C2945/76591 , B29C2945/76765 , B29C2945/76785 , B29C2945/76859 , B29K2083/005
摘要： A process and an apparatus for forming a gasket directly on a workpiece having a joining surface which has an annular gasket-fixing groove, wherein a mold having a gasket-forming groove which cooperates with the gasket-fixing groove to define a cavity for forming the gasket is clamped to the joining surface of the workpiece, and a material is injected into the cavity through an injection passage which is formed through the mold and which communicates with the gasket-forming groove. The material is cured into the gasket, and the mold is removed from the workpiece. The mold may have two elastic sealing members disposed on inner and outer sides of the gasket-forming groove, respectively, so as to extend along the gasket-forming groove, and provide pressure-tight sealing of the cavity when the body is placed on the workpiece such that the sealing members are held in elastic pressure-tight contact with the joining surface.
摘要翻译：一种用于在具有环形垫圈固定槽的接合表面的工件上直接形成垫圈的方法和装置，其中具有垫圈形成槽的模具与垫圈固定槽配合以限定用于形成衬垫被夹持在工件的接合表面上，并且材料通过通过模具形成并与衬垫形成沟槽连通的注入通道注入空腔。将材料固化到垫圈中，并将模具从工件上取下。模具可以具有分别设置在垫圈形成槽的内侧和外侧上的两个弹性密封构件，以便沿着衬垫形成槽延伸，并且当身体放置在衬垫形成槽上时提供空腔的压力密封工件，使得密封构件与接合表面保持弹性压力密封接触。

6. 发明授权

US5641692A Method for producing a Bi-MOS device 失效
标题翻译： Bi-MOS器件的制造方法
公开(公告)号：US5641692A
公开(公告)日：1997-06-24
申请号：US574363
申请日：1995-12-18
申请人： Hiroyuki Miwa , Hiroaki Anmo
发明人： Hiroyuki Miwa , Hiroaki Anmo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/265
CPC分类号： H01L21/8249 , Y10S148/009
摘要： A method for producing a semiconductor device which decrease the number of processes at the time of producing BiCMOSLSI than the usual. Impurities are introduced into a semiconductor substrate under a second insulating film and a first electric conductive film utilizing a first insulating film and the first conductive film formed on the semiconductor substrate as masks. Therefore, it is able to perform concurrent introduction of impurities into the gate electrode, the source and the drain of the MOSFET, the base electrode of the bipolar transistor, the emitter and the collector contact of the lateral bipolar transistor, the outlet electrode of the capacitor, and the resistor, so that the number of process steps can be reduced.
摘要翻译：一种半导体器件的制造方法，其减少生产BiCMOSLSI时的处理次数。杂质在第二绝缘膜和第一导电膜的第二绝缘膜之下引入到半导体衬底中，并且第一导电膜利用第一绝缘膜和形成在半导体衬底上的第一导电膜作为掩模。因此，能够同时引入杂质到栅电极，MOSFET的源极和漏极，双极晶体管的基极，横向双极晶体管的发射极和集电极接触，电容器和电阻器，从而可以减少工艺步骤的数量。

7. 发明授权

US5352624A SOI type semiconductor device and manufacturing method therefor 失效
标题翻译： SOI型半导体器件及其制造方法
公开(公告)号：US5352624A
公开(公告)日：1994-10-04
申请号：US007232
申请日：1993-01-21
申请人： Hiroyuki Miwa , Norikazu Ouchi
发明人： Hiroyuki Miwa , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/73 , H01L29/786 , H01L21/86
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/7317 , H01L29/78648
摘要： A lateral bipolar transistor including a transistor forming region provided on an insulating substrate; a first impurity diffusing region provided on the insulating substrate on one side of the transistor forming region; an emitter region formed in a first portion of the transistor forming region adjacent to the first impurity diffusing region, the emitter region being formed by diffusing a first conduction type of impurity from the first impurity diffusing region into the first portion of the transistor forming region; a base region formed in a second portion of the transistor forming region adjacent to the emitter region, the base region being formed by diffusing a second conduction type of impurity from the first impurity diffusing region into the second portion of the transistor forming region; and a collector region formed in a third portion of the transistor forming region adjacent to the base region. Accordingly, a base width can be reduced, and a dimensional accuracy of the base width can be improved.
摘要翻译：一种横向双极晶体管，包括设置在绝缘基板上的晶体管形成区域; 设置在所述晶体管形成区域一侧的所述绝缘基板上的第一杂质扩散区域; 形成在与第一杂质扩散区相邻的晶体管形成区域的第一部分中的发射极区域，通过将第一导电型杂质从第一杂质扩散区域扩散到晶体管形成区域的第一部分而形成发射极区域; 形成在与发射极区域相邻的晶体管形成区域的第二部分中的基极区域，所述基极区域通过将第二导电类型的杂质从所述第一杂质扩散区域扩散到所述晶体管形成区域的所述第二部分而形成; 以及形成在与基极区域相邻的晶体管形成区域的第三部分中的集电极区域。因此，可以减小基部宽度，并且可以提高基部宽度的尺寸精度。

8. 发明授权

US5232861A Method of manufacturing semiconductor device including a bipolar transistor 失效
标题翻译：制造包括双极晶体管的半导体器件的方法
公开(公告)号：US5232861A
公开(公告)日：1993-08-03
申请号：US751080
申请日：1991-08-28
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L29/73 , H01L21/331 , H01L21/336 , H01L29/732
CPC分类号： H01L29/66553 , H01L29/41783 , H01L29/66272 , H01L29/66575
摘要： The present invention is directed to a method of manufacturing a semiconductor device which comprises the steps of forming an opening portion through a polycide film and an insulating film sequentially formed on a semiconductor substrate of a first conductivity type so as to expose the semiconductor substrate, forming an insulating film on the side surface of the opening portion and the surface of the semiconductor substrate implanting an ion of a second conductivity type into the semiconductor substrate through the insulating film, and forming an insulating side wall in the opening portion. Thus, a metal pollution or the like in the active region due to a metal included in the polycide film can be prevented and a semiconductor device of high performance and high reliability can be manufactured. Also, the present invention is directed to a method of manufacturing a semiconductor device which comprises the steps of laminating two kinds of insulating films on a semiconductor substrate, forming a stepped opening portion for contact composed of a first opening portion through which the semiconductor substrate is exposed and a second opening portion, communicating to the first opening portion, formed by selectively removing only the upper insulating film, and burying a conductor in the stepped opening portion. Therefore, the contact widths can be reduced more and as a consequence, a semiconductor device of high performance and high reliability can be manufactured.
摘要翻译：本发明涉及一种制造半导体器件的方法，其包括以下步骤：通过依次形成在第一导电类型的半导体衬底上的多晶硅膜和绝缘膜形成开口部分，以暴露半导体衬底，形成在所述开口部的侧面的绝缘膜和所述半导体基板的表面，通过所述绝缘膜向所述半导体基板中注入第二导电型离子，在所述开口部形成绝缘侧壁。因此，可以防止由于在多硅化物膜中包含的金属而导致的有源区域中的金属污染等，并且可以制造高性能和高可靠性的半导体器件。另外，本发明涉及一种制造半导体器件的方法，该方法包括以下步骤：在半导体衬底上层压两种绝缘膜，形成用于接触的阶梯式开口部分，该第一开口部分由半导体衬底暴露的第二开口部和与第一开口部连通的第二开口部，通过仅选择性地除去上绝缘膜而形成，并且将导体埋入阶梯状开口部。因此，可以更多地减小接触宽度，结果可以制造高性能和高可靠性的半导体器件。

9. 发明授权

US06548873B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US06548873B2
公开(公告)日：2003-04-15
申请号：US09416259
申请日：1999-10-12
申请人： Hiroaki Ammo , Hiroyuki Miwa , Shigeru Kanematsu
发明人： Hiroaki Ammo , Hiroyuki Miwa , Shigeru Kanematsu
IPC分类号： H01L2976
CPC分类号： H01L21/8249 , H01L27/0635
摘要： A semiconductor device causes less element characteristic fluctuation and hardly causes parasitic actions even when a wire having a barrier metal made of a titanium material is provided. The semiconductor device includes a MOS transistor provided on the surface side of a semiconductor substrate, a first silicon oxide film, a silicon nitride film and a second silicon oxide film provided on the semiconductor substrate while covering the MOS transistor, and a wire having a barrier metal made of titanium material and provided on the insulating film, wherein the silicon nitride film covers the MOS transistor and has an opening on an element isolating region for isolating the MOS transistors. The silicon nitride film is formed in one and the same process as that of a dielectric film of a capacitor element.
摘要翻译：即使提供具有由钛材料制成的阻挡金属的导线，半导体器件引起较少的元件特性波动并且几乎不引起寄生作用。半导体器件包括设置在半导体衬底的表面侧的MOS晶体管，设置在半导体衬底上的第一氧化硅膜，氮化硅膜和第二氧化硅膜，同时覆盖MOS晶体管，以及具有阻挡层金属由钛材料制成并设置在绝缘膜上，其中氮化硅膜覆盖MOS晶体管，并且在用于隔离MOS晶体管的元件隔离区上具有开口。氮化硅膜以与电容器元件的电介质膜一样的方式形成。

10. 发明授权

US5824589A Method for forming bipolar transistor having a reduced base transit time 失效
标题翻译：具有降低的基本通行时间的形成双极晶体管的方法
公开(公告)号：US5824589A
公开(公告)日：1998-10-20
申请号：US915729
申请日：1997-08-21
申请人： Hiroyuki Miwa
发明人： Hiroyuki Miwa
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/732
CPC分类号： H01L29/1004 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A bipolar transistor has a performance and high reliability, which are by enhancing a withstand voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, a first conductive film connected to the first diffusion layer, and an opening disposed in the first conductive film. A second impurity diffusion layer is formed in a portion, exposed from the opening portion, of the semiconducting substrate and is connected to the first impurity diffusion layer. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer is formed in the third impurity diffusion layer in the opening surrounded by the side walls.
摘要翻译：双极晶体管具有通过增强发射极和基极之间的耐受电压的性能和高可靠性。双极晶体管包括在半导体衬底中的第一杂质扩散层，连接到第一扩散层的第一导电膜和设置在第一导电膜中的开口。第二杂质扩散层形成在从半导体衬底的开口部露出的部分中，并连接到第一杂质扩散层。形成第三杂质扩散层以便容纳第二扩散层，并且在开口的侧壁上形成侧壁。在由侧壁包围的开口中的第三杂质扩散层中形成第四杂质扩散层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式