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    • 9. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US08159873B2
    • 2012-04-17
    • US12513750
    • 2007-10-29
    • Mitsue TakahashiShigeki Sakai
    • Mitsue TakahashiShigeki Sakai
    • G11C11/34
    • H03K19/0185G11C11/22G11C11/223G11C14/00H01L21/28291H01L27/105H01L27/11585H01L27/1159H01L27/11592H01L29/78391
    • There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit. The state detection enhancement circuit is a positive or negative logical state detection enhancement circuit which includes a control signal terminal and a switch circuit which is turned on or off by a control signal applied to the control signal terminal, and has a function of either applying an output potential of the same logical state as or an inverse logical state of an input potential applied to the input terminal to the output terminal or completely breaking off a correlation between the input potential and the output potential when the switch circuit is in an OFF state, and has a function of applying an output potential which has the same logical state as or an inverse logical state of the input potential and has a larger highest-lowest potential range including a possible highest-lowest potential range of the input potential to the output terminal when the switch is in an ON state.
    • 提供了一种包括状态检测增强电路的半导体集成电路,其包括输入端子和输出端子,并且具有基于电位产生能够进行非易失性存储器写入非易失性存储器电路的幅度的电位的功能 输入到输入端子并将大小的电位输出到输出端子,非易失性存储器电路具有非易失性存储功能,并且非易失性存储器电路的输入端子连接到状态检测增强电路的输出端。 状态检测增强电路是正或负逻辑状态检测增强电路,其包括控制信号端子和通过施加到控制信号端子的控制信号而导通或截止的开关电路,并且具有应用 与输入端子施加到输出端子的输入电位相同的逻辑状态的输出电位或反逻辑状态,或者当开关电路处于OFF状态时完全中断输入电位与输出电位之间的相关性, 并且具有施加与输入电位具有相同逻辑状态或相反逻辑状态的输出电位的功能,并且具有包括输入电位的可能最高最低电位范围的较大最高 - 最低电位范围到输出端 当开关处于ON状态时。