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1. 发明授权

US5537354A Semiconductor memory device and method of forming the same 失效
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US5537354A
公开(公告)日：1996-07-16
申请号：US357307
申请日：1994-12-14
申请人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Hiroyoshi Tomita
发明人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Hiroyoshi Tomita
IPC分类号： G11C11/401 , F02B75/02 , G11C7/10 , G11C11/407 , G11C11/409 , G11C13/00
CPC分类号： G11C7/1072 , F02B2075/025
摘要： A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.
摘要翻译：将SDRAM（同步动态随机存取存储器）制成低速型或高速型的方法包括以下步骤：确定SDRAM的预定电极的电连接，并为预定电极提供电压由电气连接限定的电平，电压电平确定SDRAM是低速型还是高速型，其中低速类型可以以低时钟速率对具有相同的行地址，并且高速类型可以以具有相同行地址和连续列地址的两个地址以高时钟速率执行同时写入操作。

2. 发明授权

US5767712A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5767712A
公开(公告)日：1998-06-16
申请号：US892066
申请日：1997-07-14
申请人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
发明人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
IPC分类号： G06F1/04 , G11C7/22 , H01L27/02 , H03K3/356 , H03K5/13 , H03K5/1534 , H03K5/24 , H03L7/00
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , H03K3/356113 , H03K3/356156 , H03K5/133 , H03K5/1534 , H03K5/249
摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.
摘要翻译：一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟的周期时间获得特定时间信号，以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

3. 发明授权

US06166992A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06166992A
公开(公告)日：2000-12-26
申请号：US517338
申请日：2000-03-02
申请人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
发明人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
IPC分类号： G06F1/04 , G11C7/22 , H01L27/02 , H03K3/356 , H03K5/13 , H03K5/1534 , H03K5/24 , G11C8/00
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , H03K3/356113 , H03K3/356156 , H03K5/133 , H03K5/1534 , H03K5/249
摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.
摘要翻译：一种半导体器件包括：单触发脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟的周期时间来自单触发脉冲发生电路输出的单触发脉冲的信号;内部时钟发生电路，其基于由周期时间测量电路测量的周期时间和从一个脉冲发生电路输出的单次脉冲产生第二时钟信号 -shot脉冲发生电路。第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

4. 发明授权

US6009039A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US6009039A
公开(公告)日：1999-12-28
申请号：US14976
申请日：1998-01-28
申请人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
发明人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
IPC分类号： G06F1/04 , G11C7/22 , H03K3/356 , H03K5/13 , H03K5/1534 , H03K5/24 , G11C8/00 , G11C16/04
CPC分类号： G11C7/222 , G06F1/04 , G11C7/22 , H03K3/356113 , H03K3/356156 , H03K5/133 , H03K5/1534 , H03K5/249 , G11C7/04
摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.
摘要翻译：一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。

5. 发明授权

US5483497A Semiconductor memory having a plurality of banks usable in a plurality of bank configurations 失效
标题翻译：半导体存储器，具有可在多个存储体配置中使用的多个存储体
公开(公告)号：US5483497A
公开(公告)日：1996-01-09
申请号：US277486
申请日：1994-07-19
申请人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Katsumi Shigenobu
发明人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Katsumi Shigenobu
IPC分类号： G11C11/41 , G06F12/06 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C7/00
CPC分类号： G06F12/0623 , G11C8/12
摘要： A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.
摘要翻译：具有多个存储体的半导体存储器，第一指定单元和第二指定单元。第一指定单元用于通过解码包含在行地址信号中的存储体地址信号来指定存储体之一。第二指定单元用于根据指示每个存储体是否被激活的存储体状态信号对包含在行地址信号中的存储体地址信号进行解码来指定存储区之一。因此，半导体存储器用于不同的存储体配置。也就是说，通过这种布置，半导体存储器能够用作具有较少数量的存储体的存储器，从而提高方便性。

6. 发明授权

US5535169A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5535169A
公开(公告)日：1996-07-09
申请号：US322564
申请日：1994-10-13
申请人： Tetsuya Endo , Hirohiko Mochizuki , Yukinori Kodama , Yoshihiro Takemae
发明人： Tetsuya Endo , Hirohiko Mochizuki , Yukinori Kodama , Yoshihiro Takemae
IPC分类号： G11C11/406 , G11C11/407 , G11C8/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device includes a plurality of banks each having a memory cell array and sense amplifiers, a data input/output circuit and an address circuit. A first part of the device receives control signals from an outside of the semiconductor memory device and generates a refresh signal therefrom. A second part generates bank select signals in response to the refresh signal, the bank select signals being used to select the plurality of banks. A third part receives the bank select signals and generating latch enable signals therefrom, the latch enable signals driving the sense amplifiers provided in the plurality of banks. A refresh operation is carried out by activating the sense amplifiers by using the latch enable signals.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元具有存储单元阵列和读出放大器，数据输入/输出电路和地址电路。设备的第一部分从半导体存储器件的外部接收控制信号并从其产生刷新信号。第二部分响应于刷新信号产生存储体选择信号，存储体选择信号用于选择多个存储体。第三部分接收存储体选择信号并产生锁存使能信号，锁存器使能信号驱动设置在多个存储体中的读出放大器。通过使用锁存使能信号来激活读出放大器来进行刷新操作。

7. 发明授权

US6154405A Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data 失效
标题翻译：具有虚设单元的半导体存储器件，其将位线复位为基于在先前读取数据中读取的数据的复位电位
公开(公告)号：US6154405A
公开(公告)日：2000-11-28
申请号：US924315
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/401 , G11C11/407 , G11C11/4096 , G11C7/02
CPC分类号： G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.
摘要翻译：半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。

8. 发明授权

US6151274A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 有权
标题翻译：由同步半导体器件构成的系统，用于调整每个输入端和用于其的半导体器件的时序
公开(公告)号：US6151274A
公开(公告)日：2000-11-21
申请号：US440665
申请日：1999-11-16
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.
摘要翻译：公开了一种用于实现这种系统的系统和半导体器件。该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据可以高速转移。在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

9. 发明授权

US6028816A System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor 失效
公开(公告)号：US6028816A
公开(公告)日：2000-02-22
申请号：US924705
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

10. 发明授权

US4413272A Semiconductor devices having fuses 失效
标题翻译：具有保险丝的半导体器件
公开(公告)号：US4413272A
公开(公告)日：1983-11-01
申请号：US183734
申请日：1980-09-03
申请人： Hirohiko Mochizuki , Masao Nakano , Fumio Baba , Tomio Nakano , Yoshihiro Takemae
发明人： Hirohiko Mochizuki , Masao Nakano , Fumio Baba , Tomio Nakano , Yoshihiro Takemae
IPC分类号： G11C17/06 , G11C17/00 , G11C17/14 , G11C17/16 , H01L23/50 , H01L23/52 , H01L23/525 , H01L23/62
CPC分类号： G11C17/16 , H01L23/5256 , H01L23/62 , H01L2924/0002
摘要： A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.
摘要翻译：半导体存储器件具有涂覆有保护层的保险丝。选择性地蚀刻保护层以打开窗口，以便露出保险丝的中心部分。在中心窗口打开之后，执行保险丝的熔合操作以在熔断体的中心窗部分中打开间隙。在优选实施例中，然后添加另一保护层以填充熔断保险丝中的间隙。

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