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1. 发明授权

US06770517B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06770517B2
公开(公告)日：2004-08-03
申请号：US10028803
申请日：2001-12-28
申请人： Hiroaki Nakaoka , Hiromasa Fujimoto , Atsushi Hori , Takashi Uehara , Takehiro Hirai
发明人： Hiroaki Nakaoka , Hiromasa Fujimoto , Atsushi Hori , Takashi Uehara , Takehiro Hirai
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78621 , Y10S438/91
摘要： In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions. Thus, it is possible to provide an SOI transistor causing no decrease in the source/drain breakdown voltage resulting from substrate floating effects and causing little OFF leakage current because of the activation of the parasitic transistor.
摘要翻译：在形成在绝缘体层上的硅层中，形成与沟道区域和源极/漏极区域相邻的晶格缺陷区域，沟道区域的下部部分作为高浓度沟道区域。通过在晶格缺陷区域中的复合消除在沟道区域中产生的空穴 - 电子对的空穴，从而抑制由于空穴的积累而产生的双极性运算并增加源极/漏极击穿电压。寄生晶体管的阈值由高浓度沟道区域增加，以便在OFF状态下减少漏电流。或者，可以通过提供构成并在沟道和源极区域之间作为pn二极管工作的高浓度扩散层而不是晶格缺陷区域，而将孔移动到源极区域以消失。因此，可以提供一种SOI晶体管，其不会由于衬底浮置效应而导致的源极/漏极击穿电压降低，并且由于寄生晶体管的激活而导致小的漏电流。

2. 发明授权

US06337500B1 Semiconductor device and method for fabricating the same 失效
公开(公告)号：US06337500B1
公开(公告)日：2002-01-08
申请号：US09099195
申请日：1998-06-18
申请人： Hiroaki Nakaoka , Hiromasa Fujimoto , Atsushi Hori , Takashi Uehara , Takehiro Hirai
发明人： Hiroaki Nakaoka , Hiromasa Fujimoto , Atsushi Hori , Takashi Uehara , Takehiro Hirai
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78612 , H01L29/78621 , Y10S438/91
摘要： In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions. Thus, it is possible to provide an SOI transistor causing no decrease in the source/drain breakdown voltage resulting from substrate floating effects and causing little OFF leakage current because of the activation of the parasitic transistor.

3. 发明申请

US20050161745A1 CMOS device, method for fabricating the same and method for generating mask data 审中-公开
标题翻译： CMOS器件，其制造方法以及用于生成掩模数据的方法
公开(公告)号：US20050161745A1
公开(公告)日：2005-07-28
申请号：US11028526
申请日：2005-01-05
申请人： Tokuhiko Tamaki , Hiromasa Fujimoto , Takatoshi Yasui , Takehiro Hirai
发明人： Tokuhiko Tamaki , Hiromasa Fujimoto , Takatoshi Yasui , Takehiro Hirai
IPC分类号： G03F1/20 , H01L21/266 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/76 , H01L31/062
CPC分类号： H01L21/823842
摘要： An NMIS gate implantation layer is generated by a method in which mask data of a P-type well implantation layer are added to mask data obtained by subtracting mask data of an NMIS-SD implantation layer and PMIS-SD implantation layer from mask data of an N-type well implantation layer. In a CMOS device fabricating process, ions are implanted into a polysilicon film by using the NMIS gate implantation layer, resulting in reduction in the total numbers of PN junctions and non-doped regions in a gate polysilicon film.
摘要翻译：通过将P型阱注入层的掩模数据添加到通过从掩模数据中减去NMIS-SD注入层和PMIS-SD注入层的掩模数据而获得的掩模数据的方法来产生NMIS栅极注入层 N型井注入层。在CMOS器件制造工艺中，通过使用NMIS栅极注入层将离子注入到多晶硅膜中，导致栅极多晶硅膜中PN结和非掺杂区域的总数减少。

4. 发明授权

US07932141B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07932141B2
公开(公告)日：2011-04-26
申请号：US12164635
申请日：2008-06-30
申请人： Kentaro Nakanishi , Hiromasa Fujimoto , Takayuki Yamada
发明人： Kentaro Nakanishi , Hiromasa Fujimoto , Takayuki Yamada
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.
摘要翻译：半导体器件包括n型MIS晶体管和p型MIS晶体管。 n型MIS晶体管包括形成在第一有源区上的第一栅电极和形成在第一栅电极的侧面上的第一侧壁。 p型MIS晶体管包括形成在第二有源区上的第二栅电极，形成在第二栅电极的侧面上的第二侧壁和形成在第二有源区中的应变层。第二侧壁具有比第一侧壁更小的厚度。

5. 发明授权

US06830973B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06830973B2
公开(公告)日：2004-12-14
申请号：US10238636
申请日：2002-09-11
申请人： Hiromasa Fujimoto , Fumihiko Noro , Masataka Kusumi
发明人： Hiromasa Fujimoto , Fumihiko Noro , Masataka Kusumi
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.
摘要翻译：使用快速热氧化装置，浮栅电极的顶表面和侧表面被原位蒸汽发生（ISSG）氧化，其中加入约0.5％至33％氢的氧气直接引入具有温度约900至1100℃，压力为约1,000至2,000Pa，以便在加热的半导体衬底上从引入的氢气和氧气产生水蒸汽。因此，在浮栅电极的表面上形成由氧化硅制成的绝缘膜。

6. 发明授权

US06784040B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06784040B2
公开(公告)日：2004-08-31
申请号：US10382508
申请日：2003-03-07
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
摘要翻译：非易失性半导体存储器件具有沉积在控制栅电极的每个侧表面上的保护绝缘膜，以在形成浮栅电极期间保护控制栅电极，浮置栅极与其中一个侧表面相对控制栅电极，其间插入有保护绝缘膜，以便电容耦合到控制栅电极，形成在浮置栅电极和半导体衬底之间的隧道绝缘膜，形成在半导体衬底的包含并且形成在半导体衬底的与漏极区相对的控制栅电极相对的区域中的源极区。

7. 发明授权

US08178929B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08178929B2
公开(公告)日：2012-05-15
申请号：US13052546
申请日：2011-03-21
申请人： Kentaro Nakanishi , Hiromasa Fujimoto , Takayuki Yamada
发明人： Kentaro Nakanishi , Hiromasa Fujimoto , Takayuki Yamada
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.
摘要翻译：半导体器件包括n型MIS晶体管和p型MIS晶体管。 n型MIS晶体管包括形成在第一有源区上的第一栅电极和形成在第一栅电极的侧面上的第一侧壁。 p型MIS晶体管包括形成在第二有源区上的第二栅电极，形成在第二栅电极的侧面上的第二侧壁和形成在第二有源区中的应变层。第二侧壁具有比第一侧壁更小的厚度。

8. 发明授权

US08035150B2 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08035150B2
公开(公告)日：2011-10-11
申请号：US11563417
申请日：2006-11-27
申请人： Hiromasa Fujimoto
发明人： Hiromasa Fujimoto
IPC分类号： H01L29/768 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.
摘要翻译： NOR型闪速存储器的存储单元阵列是通过将存储单元晶体管布置在矩阵中而构成的，每个存储单元晶体管包括将半导体衬底连接到覆盖线的触点。存储单元晶体管的列通过浅沟槽隔离彼此隔离。与每个漏极接触相邻的浅沟槽隔离物中的填充氧化膜的顶表面的高度等于漏区的顶表面的高度。与沟道区相邻的浅沟槽隔离中的填充氧化膜的顶面高于沟道区的半导体衬底的上表面。

9. 发明授权

US06545312B2 Nonvolatile semiconductor memory device and method for fabricating the same 有权
公开(公告)号：US06545312B2
公开(公告)日：2003-04-08
申请号：US09897417
申请日：2001-07-03
申请人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
发明人： Masataka Kusumi , Fumihiko Noro , Hiromasa Fujimoto , Akihiro Kamada , Shinji Odanaka , Seiki Ogura
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

10. 发明授权

US08779524B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08779524B2
公开(公告)日：2014-07-15
申请号：US13554386
申请日：2012-07-20
申请人： Yoshiya Moriyama , Hiromasa Fujimoto , Satoru Itou , Susumu Akamatsu , Hiroshi Ohkawa
发明人： Yoshiya Moriyama , Hiromasa Fujimoto , Satoru Itou , Susumu Akamatsu , Hiroshi Ohkawa
IPC分类号： H01L27/092 , H01L29/78 , H01L21/768 , H01L21/28
CPC分类号： H01L29/7843 , H01L21/28123 , H01L21/28176 , H01L21/76895 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L23/485 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1
摘要翻译：半导体器件包括第一导电型第一MIS晶体管和第二导电型第二MIS晶体管。第一和第二MIS晶体管包括形成在由半导体衬底的分离区围绕的第一和第二有源区上的第一和第二栅极绝缘膜，以及形成在第一和第二栅极绝缘上的第一和第二栅电极电影。第一和第二栅极绝缘膜在分离区域的第一分离区域上彼此分离。在第一和第二有源区域的第一端之间的距离为第一和第二有源区域之间的距离，第一分隔区域彼此相对，并且从第一有源区域的第一端到第一栅极绝缘膜的第一端的突出量d1 在第一分离区域建立关系d1 <0.5s。

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