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1. 发明授权

US08077492B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08077492B2
公开(公告)日：2011-12-13
申请号：US12268017
申请日：2008-11-10
申请人： Katsumi Dosaka , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
发明人： Katsumi Dosaka , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。匹配线用作水平位线对或用于访问水平端口的信号线。当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。

2. 发明申请

US20100308858A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SIGNAL PROCESSING APPARATUS 失效
标题翻译：半导体器件和半导体信号处理装置
公开(公告)号：US20100308858A1
公开(公告)日：2010-12-09
申请号：US12857063
申请日：2010-08-16
申请人： Hideyuki NODA , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki NODA , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： H03K19/003
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

3. 发明授权

US07791962B2 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US07791962B2
公开(公告)日：2010-09-07
申请号：US12213131
申请日：2008-06-16
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G11C7/10
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

4. 发明申请

US20090027978A1 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US20090027978A1
公开(公告)日：2009-01-29
申请号：US12213131
申请日：2008-06-16
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G11C7/10
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

5. 发明申请

US20070245168A1 Associative memory capable of searching for data while keeping high data reliability 审中-公开
公开(公告)号：US20070245168A1
公开(公告)日：2007-10-18
申请号：US11798022
申请日：2007-05-09
申请人： Hideyuki Noda , Katsumi Dosaka
发明人： Hideyuki Noda , Katsumi Dosaka
IPC分类号： G06F11/16
CPC分类号： G06F11/1064 , G06F11/00 , G11C15/00 , G11C15/043
摘要： A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check bits to correct any error of data read from the memory array of the RAM unit and rewrite the error-corrected data to the memory arrays. Even if a soft error occurs in the storage data, the check bits can be used to correct the error in the data and rewrite the error-corrected data. Thus, a matching comparison can be performed on the storage data with high reliability.

6. 发明授权

US07505352B2 Parallel operational processing device 失效
标题翻译：并行运行处理装置
公开(公告)号：US07505352B2
公开(公告)日：2009-03-17
申请号：US11698188
申请日：2007-01-26
申请人： Takayuki Gyoten , Katsumi Dosaka , Hideyuki Noda , Tetsushi Tanizaki
发明人： Takayuki Gyoten , Katsumi Dosaka , Hideyuki Noda , Tetsushi Tanizaki
IPC分类号： G11C8/00 , G11C5/06 , G11C7/00
CPC分类号： G06F13/1652 , G11C7/1006 , Y02D10/14
摘要： In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.
摘要翻译：在并行运算处理装置中，具有布置在各自具有排列成行和列的多个存储单元的存储块之间的运算处理单元，各存储块的各列交替地与存储器的相对侧的运算处理单元连接块。通过在一个存储器块中选择一个字线，可以将数据传输到两个操作处理单元。每个操作处理单元选择的字线数减少，功耗降低。操作处理单元的位操作单元和读出放大器/写驱动器具有减轻的布置节距条件，并且数量减少，并且不需要存储器块之间的隔离区域，并且布局面积减小。因此，具有布局面积和功耗降低的并行运算处理装置可以实现快速运行。

7. 发明授权

US07463501B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07463501B2
公开(公告)日：2008-12-09
申请号：US11517441
申请日：2006-09-08
申请人： Katsumi Dosaka , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
发明人： Katsumi Dosaka , Kazutami Arimoto , Kazunori Saito , Hideyuki Noda
IPC分类号： G11C7/00
CPC分类号： G11C15/04 , G11C15/00
摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.
摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。匹配线用作水平位线对或用于访问水平端口的信号线。当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。

8. 发明申请

US20050285862A1 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US20050285862A1
公开(公告)日：2005-12-29
申请号：US11148369
申请日：2005-06-09
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G06F15/16 , G11C7/10
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

9. 发明授权

US08089819B2 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US08089819B2
公开(公告)日：2012-01-03
申请号：US12857063
申请日：2010-08-16
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Arimoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Arimoto , Katsumi Dosaka
IPC分类号： G11C7/06
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

10. 发明授权

US07562198B2 Semiconductor device and semiconductor signal processing apparatus 失效
公开(公告)号：US07562198B2
公开(公告)日：2009-07-14
申请号：US11148369
申请日：2005-06-09
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G06F21/22
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

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