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1. 发明申请

US20090027978A1 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US20090027978A1
公开(公告)日：2009-01-29
申请号：US12213131
申请日：2008-06-16
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G11C7/10
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

2. 发明授权

US07562198B2 Semiconductor device and semiconductor signal processing apparatus 失效
公开(公告)号：US07562198B2
公开(公告)日：2009-07-14
申请号：US11148369
申请日：2005-06-09
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G06F21/22
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

3. 发明申请

US20050285862A1 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US20050285862A1
公开(公告)日：2005-12-29
申请号：US11148369
申请日：2005-06-09
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G06F15/16 , G11C7/10
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

4. 发明申请

US20100308858A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SIGNAL PROCESSING APPARATUS 失效
标题翻译：半导体器件和半导体信号处理装置
公开(公告)号：US20100308858A1
公开(公告)日：2010-12-09
申请号：US12857063
申请日：2010-08-16
申请人： Hideyuki NODA , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki NODA , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： H03K19/003
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

5. 发明授权

US07791962B2 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US07791962B2
公开(公告)日：2010-09-07
申请号：US12213131
申请日：2008-06-16
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Ariomoto , Katsumi Dosaka
IPC分类号： G11C7/10
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

6. 发明授权

US08089819B2 Semiconductor device and semiconductor signal processing apparatus 失效
标题翻译：半导体装置及半导体信号处理装置
公开(公告)号：US08089819B2
公开(公告)日：2012-01-03
申请号：US12857063
申请日：2010-08-16
申请人： Hideyuki Noda , Kazunori Saitoh , Kazutami Arimoto , Katsumi Dosaka
发明人： Hideyuki Noda , Kazunori Saitoh , Kazutami Arimoto , Katsumi Dosaka
IPC分类号： G11C7/06
CPC分类号： G11C7/1006
摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
摘要翻译：存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。

7. 发明授权

US07720127B2 Opto-semiconductor devices 有权
标题翻译：光电半导体器件
公开(公告)号：US07720127B2
公开(公告)日：2010-05-18
申请号：US12232652
申请日：2008-09-22
申请人： Yutaka Inoue , Kazunori Saitoh , Hiroshi Hamada , Masato Hagimoto , Susumu Sorimachi
发明人： Yutaka Inoue , Kazunori Saitoh , Hiroshi Hamada , Masato Hagimoto , Susumu Sorimachi
IPC分类号： H01S3/097
CPC分类号： H01S5/0224 , B82Y20/00 , H01S5/02212 , H01S5/02272 , H01S5/02476 , H01S5/0425 , H01S5/16 , H01S5/2081 , H01S5/22 , H01S5/34326 , H01S2301/14
摘要： An opto-semiconductor device. An opto-semiconductor element includes a semiconductor substrate, a multilayered semiconductor layer formed on a first surface of the semiconductor substrate and having a resonator, a first electrode with multiple conductive layers formed on the multilayered semiconductor layer, and a second electrode formed on a second surface of the semiconductor substrate. A support substrate has a first surface formed with a fixing portion having a conductive layer for fixing the first electrode connected thereto through a bonding material. Bonding material and conductive layers forming the first electrode react to form a reaction layer. The difference in thermal expansion coefficient between semiconductor substrate and support substrate is not more than ±50%. A second barrier metal layer not reactive with bonding material is formed inside the first electrode uppermost conductive layer, while uppermost layer reacts with the bonding material to form the reaction layer.
摘要翻译：光电半导体器件。光半导体元件包括半导体衬底，形成在半导体衬底的第一表面上并具有谐振器的多层半导体层，形成在多层半导体层上的多个导电层的第一电极和形成在第二层上的第二电极半导体衬底的表面。支撑基板具有形成有固定部的第一表面，该固定部具有用于通过接合材料固定与其连接的第一电极的导电层。形成第一电极的接合材料和导电层反应形成反应层。半导体衬底和支撑衬底之间的热膨胀系数差不超过±50％。在第一电极最上层的导电层的内部形成与接合材料不反应的第二阻挡金属层，而最上层与接合材料反应形成反应层。

8. 发明授权

US06192011B1 Gain controlling apparatus and method, information reproducing apparatus and method, and information recording apparatus and method 失效
标题翻译：增益控制装置和方法，信息再现装置和方法以及信息记录装置和方法
公开(公告)号：US06192011B1
公开(公告)日：2001-02-20
申请号：US09443137
申请日：1999-11-19
申请人： Kazuhiro Kiyoura , Toshiyuki Suzuki , Takeshi Matsumoto , Hiroshi Kitagawa , Takehiro Takada , Kazunori Saitoh
发明人： Kazuhiro Kiyoura , Toshiyuki Suzuki , Takeshi Matsumoto , Hiroshi Kitagawa , Takehiro Takada , Kazunori Saitoh
IPC分类号： G11B700
CPC分类号： G11B7/005 , G11B7/0945 , G11B20/10009
摘要： A gain controlling apparatus is provided with: an adjusting device (6, 7, 8) for adjusting a gain of a generation signal, which is generated on the basis of a light reception signal obtained by receiving a reflection light of a light beam from an information recording medium (1); and a detecting device (21, 14, 16) for detecting whether or not the generation signal is generated and outputting a detection signal when the generation signal is generated. The gain controlling apparatus is also provided with a controlling device (18) for controlling the adjusting device to increase the gain by a predetermined value set in advance when the detection signal is not outputted by the detecting device.
摘要翻译：一种增益控制装置，具备：调整装置（6,7,8），用于调整发电信号的增益，该调整装置是根据通过接收来自光源的光束的反射光而得到的光接收信号信息记录介质（1）; 和检测装置（21,14,16），用于检测生成信号是否产生，并在生成信号时输出检测信号。增益控制装置还具有控制装置（18），用于当检测装置未输出检测信号时，控制调节装置将增益增加预先设定的预定值。

9. 发明申请

US20060004723A1 Device, method, and computer product for reading tag data included in compressed data file 审中-公开
标题翻译：用于读取包含在压缩数据文件中的标签数据的设备，方法和计算机产品
公开(公告)号：US20060004723A1
公开(公告)日：2006-01-05
申请号：US11138315
申请日：2005-05-27
申请人： Akihito Fujiwara , Seiji Nakano , Masakazu Takahashi , Hiroyuki Akama , Kazunori Saitoh , Kazushige Kawana , Akihiro Hashimoto
发明人： Akihito Fujiwara , Seiji Nakano , Masakazu Takahashi , Hiroyuki Akama , Kazunori Saitoh , Kazushige Kawana , Akihiro Hashimoto
IPC分类号： G06F17/30
CPC分类号： H04N21/435 , G06F16/68 , G10L19/167 , H04N21/235 , H04N21/439 , H04N21/44 , H04N21/8173 , H04N21/8405
摘要： A method for reading tag data is provided, involving reading a compressed data file that includes compressed data and tag data of a fixed length appended to the compressed data at a predetermined position, and performing a predetermined process based on the type of the compressed data. The reading process of the compressed data file includes first searching for the starting position of the tag data of the compressed data file and retrieving the tag data, followed by searching for the starting position of the compressed data.
摘要翻译：提供了一种用于读取标签数据的方法，涉及在预定位置读取包含附加到压缩数据的固定长度的压缩数据和标签数据的压缩数据文件，并且基于压缩数据的类型执行预定处理。压缩数据文件的读取处理包括首先搜索压缩数据文件的标签数据的起始位置并检索标签数据，然后搜索压缩数据的起始位置。

10. 发明授权

US06835543B2 Step agglutination immunoassay 失效
标题翻译：步骤凝集免疫测定
公开(公告)号：US06835543B2
公开(公告)日：2004-12-28
申请号：US08893759
申请日：1997-07-11
申请人： Kazunori Saitoh , Mitsuhisa Manabe
发明人： Kazunori Saitoh , Mitsuhisa Manabe
IPC分类号： G01N3353
CPC分类号： G01N33/54313 , Y10S435/962
摘要： An immunoassay for detecting an antigen in a sample, by: (a) sequentially contacting the sample with (i) a first antibody which is capable of specifically binding to a first binding site on the antigen, and then (ii) a second antibody which is capable of specifically binding to a second binding site on the antigen, thereby forming, when the antigen is present in the sample, an agglutinate comprising the first antibody, the antigen, and the second antibody; followed by (b) optically measuring the amount of the agglutinate.
摘要翻译：用于通过以下步骤检测样品中的抗原的免疫测定法：（a）使样品与（i）能够特异性结合抗原上的第一结合位点的第一抗体依次接触，然后（ii）第二抗体，能够特异性结合抗原上的第二结合位点，从而当抗原存在于样品中时形成包含第一抗体，抗原和第二抗体的凝集物; 然后（b）光学测定凝集物的量。

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