专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050193274A1 Method and apparatus for testing a memory device in quasi-operating conditions 失效
标题翻译：用于在准操作条件下测试存储器件的方法和装置
公开(公告)号：US20050193274A1
公开(公告)日：2005-09-01
申请号：US11107896
申请日：2005-04-18
申请人： Hideyuki Aoki , Takeshi Wada , Masaaki Namba , Noboru Uchida , Shigeki Katsumi , Yuji Wada , Masaaki Mochiduki
发明人： Hideyuki Aoki , Takeshi Wada , Masaaki Namba , Noboru Uchida , Shigeki Katsumi , Yuji Wada , Masaaki Mochiduki
IPC分类号： G01R31/28 , G06F12/16 , G11C29/56 , G06F11/00
CPC分类号： G11C29/56
摘要： A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer. The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out from the measurement PC unit; a plurality of PFBs mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chip set LSI on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.
摘要翻译：记忆测试系统可以通过使用个人计算机在准操作条件下以低成本准确地屏蔽测试对象。该系统利用包括测量PC单元的PC测试器，该单元携带用作参考的存储器模块; 信号分配单元，用于分配从测量PC单元取出的信号; 通过使用由信号分配单元分配的信号同时观察安装有相应对象产品的多个PFB; 用于显示正在进行的测试的当前状态的显示面板; 用于产生系统的工作电压的电源; 以及用于控制测试参数和各种分析操作的选择的控制PC。 PC测试器适于将测量PC单元中的PC母板上的芯片组LSI的信号从存储器模块或存储器模块本身的各个存储器中取出，并在准工作条件下进行测试。

2. 发明授权

US07356742B2 Method and apparatus for testing a memory device in quasi-operating conditions 失效
标题翻译：用于在准操作条件下测试存储器件的方法和装置
公开(公告)号：US07356742B2
公开(公告)日：2008-04-08
申请号：US11107896
申请日：2005-04-18
申请人： Hideyuki Aoki , Takeshi Wada , Masaaki Namba , Noboru Uchida , Shigeki Katsumi , Yuji Wada , Masaaki Mochiduki
发明人： Hideyuki Aoki , Takeshi Wada , Masaaki Namba , Noboru Uchida , Shigeki Katsumi , Yuji Wada , Masaaki Mochiduki
IPC分类号： G11C29/00
CPC分类号： G11C29/56
摘要： A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chipset LSI (large scale integrated circuit) on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.
摘要翻译：记忆测试系统可以通过使用个人计算机（PC）在准操作条件下以低成本准确地屏蔽测试对象。该系统利用包括测量PC单元的PC测试器，该单元携带用作参考的存储器模块; 信号分配单元，用于分配从测量PC单元取出的信号; 通过使用由信号分配单元分配的信号同时观察安装有相应对象产品的多个性能板（PFB）; 用于显示正在进行的测试的当前状态的显示面板; 用于产生系统的工作电压的电源; 以及用于控制测试参数和各种分析操作的选择的控制PC。 PC测试器适用于将测量PC单元中的PC母板上的芯片组LSI（大规模集成电路）的信号从存储器模块或存储器模块本身的各个存储器中取出，运行条件。

3. 发明授权

US07422914B2 Fabrication method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07422914B2
公开(公告)日：2008-09-09
申请号：US11936358
申请日：2007-11-07
申请人： Yuji Wada , Akira Seito , Masaaki Namba
发明人： Yuji Wada , Akira Seito , Masaaki Namba
IPC分类号： G01R31/26
CPC分类号： G01R31/287 , G01R31/286 , G01R31/31718 , G11C29/56 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48247 , H01L2225/06558 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.
摘要翻译：在具有效率低成本的包括半导体存储器的半导体集成电路器件上进行存储器测试。在测试老化系统中，24个测试板按时间顺序进行处理，测试板逐个循环。在这种情况下，以单板处理的顺序进行存储器测试：测试开始于已经嵌入半导体集成电路器件的测试板，半导体集成电路器件被放电，从具有经过测试

4. 发明授权

US07306957B2 Fabrication method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07306957B2
公开(公告)日：2007-12-11
申请号：US11012225
申请日：2004-12-16
申请人： Yuji Wada , Akira Seito , Masaaki Namba
发明人： Yuji Wada , Akira Seito , Masaaki Namba
IPC分类号： G01R31/26
CPC分类号： G01R31/287 , G01R31/286 , G01R31/31718 , G11C29/56 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48247 , H01L2225/06558 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.
摘要翻译：在具有效率低成本的包括半导体存储器的半导体集成电路器件上进行存储器测试。在测试老化系统中，24个测试板按时间顺序进行处理，测试板逐个循环。在这种情况下，以单板处理的顺序进行存储器测试：测试开始于已经嵌入半导体集成电路器件的测试板，半导体集成电路器件被放电，从具有经过测试

5. 发明授权

US06864568B2 Packaging device for holding a plurality of semiconductor devices to be inspected 失效
标题翻译：用于保持待检查的多个半导体器件的封装装置
公开(公告)号：US06864568B2
公开(公告)日：2005-03-08
申请号：US10252546
申请日：2002-09-24
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R31/26 , G01R1/04 , G01R1/073 , H01L21/66 , H01L23/02
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

6. 发明授权

US06696849B2 Fabrication method of semiconductor integrated circuit device and its testing apparatus 有权
标题翻译：半导体集成电路器件及其测试装置的制造方法
公开(公告)号：US06696849B2
公开(公告)日：2004-02-24
申请号：US09964708
申请日：2001-09-28
申请人： Naoto Ban , Masaaki Namba , Akio Hasebe , Yuji Wada , Ryuji Kohno , Akira Seito , Yasuhiro Motoyama
发明人： Naoto Ban , Masaaki Namba , Akio Hasebe , Yuji Wada , Ryuji Kohno , Akira Seito , Yasuhiro Motoyama
IPC分类号： G01R3102
CPC分类号： G01R31/2831
摘要： A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.
摘要翻译：一种半导体集成电路器件的测试装置和制造方法，用于通过在晶片级老化中放置与晶片的整个表面均匀接触的分割的接触器来降低制造成本，从而能够修复每个接触器并提高产量的接触器。测试装置中的机械加压系统的盒式结构由多个分开的硅接触器块和用于集成这些块的引导框架构成，并且采用分开的接触器一体化型的晶片全表面同时接触系统。硅接触器的每个探针通过机械加压每个单独移动的硅接触器块，将测试控制信号提供给每个芯片，并且测试结果与测试晶片的每个芯片的每个测试焊盘等同地以预定压力接触获得晶片级老化测试信号。

7. 发明授权

US06465264B1 Method for producing semiconductor device and apparatus usable therein 失效
标题翻译：用于制造半导体器件的方法和可用于其中的装置
公开(公告)号：US06465264B1
公开(公告)日：2002-10-15
申请号：US09654612
申请日：2000-09-01
申请人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
发明人： Ryuji Kohno , Hiroya Shimizu , Masatoshi Kanamaru , Atsushi Hosogane , Toshio Miyatake , Hideo Miura , Tatsuya Nagata , Yoshishige Endo , Masaaki Namba , Yuji Wada
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , H01L2924/0002 , H01L2924/00
摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.
摘要翻译：一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件并且延伸到包装装置的外部，使得探针连接到每个导电构件。

8. 发明申请

US20080293167A1 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20080293167A1
公开(公告)日：2008-11-27
申请号：US12184563
申请日：2008-08-01
申请人： Yuji Wada , Akira Seito , Masaaki Namba
发明人： Yuji Wada , Akira Seito , Masaaki Namba
IPC分类号： H01L21/66
CPC分类号： G01R31/287 , G01R31/286 , G01R31/31718 , G11C29/56 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48247 , H01L2225/06558 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.
摘要翻译：在具有效率低成本的包括半导体存储器的半导体集成电路器件上进行存储器测试。在测试老化系统中，24个测试板按时间顺序进行处理，测试板逐个循环。在这种情况下，以单板处理的顺序进行存储器测试：测试开始于已经嵌入半导体集成电路器件的测试板，半导体集成电路器件被放电，从具有经过测试

9. 发明申请

US20080070330A1 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：US20080070330A1
公开(公告)日：2008-03-20
申请号：US11936358
申请日：2007-11-07
申请人： Yuji Wada , Akira Seito , Masaaki Namba
发明人： Yuji Wada , Akira Seito , Masaaki Namba
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R31/287 , G01R31/286 , G01R31/31718 , G11C29/56 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48247 , H01L2225/06558 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

10. 发明申请

US20050153465A1 Fabrication method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20050153465A1
公开(公告)日：2005-07-14
申请号：US11012225
申请日：2004-12-16
申请人： Yuji Wada , Akira Seito , Masaaki Namba
发明人： Yuji Wada , Akira Seito , Masaaki Namba
IPC分类号： G01R31/26 , G01R31/28 , G11C29/56 , H01L21/66
CPC分类号： G01R31/287 , G01R31/286 , G01R31/31718 , G11C29/56 , G11C29/56016 , G11C2029/5602 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/48247 , H01L2225/06558 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.
摘要翻译：在具有效率低成本的包括半导体存储器的半导体集成电路器件上进行存储器测试。在测试老化系统中，24个测试板按时间顺序进行处理，测试板逐个循环。在这种情况下，以单板处理的顺序进行存储器测试：测试开始于已经嵌入半导体集成电路器件的测试板，半导体集成电路器件被放电，从具有经过测试

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式