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    • 7. 发明授权
    • Serial data transferring apparatus
    • 串行数据传输设备
    • US07260657B2
    • 2007-08-21
    • US10491285
    • 2001-10-02
    • Masahiro MatsumotoFumio MurabayashiHiromichi YamadaKeiji HanzawaHiroyasu Sukesako
    • Masahiro MatsumotoFumio MurabayashiHiromichi YamadaKeiji HanzawaHiroyasu Sukesako
    • G06F3/00G06F5/00
    • H04L7/10H04J3/24H04J7/00H04L7/046H04L7/06
    • A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.
    • 主单元向从单元发送启动信号。 当从主单元接收到起始信号时,从单元向主单元发送同步字段,该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串(脉冲信号) 。 主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。 响应于从主单元发送的命令数据,从单元根据由同步字段指示的传送时钟向主单元发送响应数据。 因此,在采用本发明的串行数据传送装置的通信系统中,主单元建立用于数据传送的同步,而从单元没有建立用于数据传送的同步的负担。 实现了串行数据传送装置,其可以简化从单元的结构,降低总成本并降低噪声。
    • 8. 发明申请
    • ERROR CORRECTION METHOD
    • 错误校正方法
    • US20070180317A1
    • 2007-08-02
    • US11623441
    • 2007-01-16
    • Teppei HIROTSUHiromichi YamadaTeruaki SakataKesami Hagiwara
    • Teppei HIROTSUHiromichi YamadaTeruaki SakataKesami Hagiwara
    • G06F11/00
    • G06F11/1407
    • This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
    • 该方法是一种错误校正方法,使得当在具有流水线结构的CPU中检测到错误时,通过延迟的寄存器文件来恢复寄存器文件的内容,该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态 该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。 该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果,并检测出错误。 结果,寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态,并且可以从可能由错误发生故障的指令范围的开始滚转指令 。