专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070070882A1 OFDM demodulating apparatus and method 失效
标题翻译： OFDM解调装置及方法
公开(公告)号：US20070070882A1
公开(公告)日：2007-03-29
申请号：US11489161
申请日：2006-07-19
申请人： Hidetoshi Kawauchi , Toshihisa Hyakudai , Takuya Okamoto , Atsushi Yajima , Taku Yamagata , Kazutaka Yamamoto , Shigenari Kawabata
发明人： Hidetoshi Kawauchi , Toshihisa Hyakudai , Takuya Okamoto , Atsushi Yajima , Taku Yamagata , Kazutaka Yamamoto , Shigenari Kawabata
IPC分类号： H04J11/00
CPC分类号： H04L25/0232 , H04L27/261 , H04L27/265 , H04L27/2662 , H04L27/2665
摘要： An orthogonal frequency division multiplexing (OFDM) demodulating apparatus includes a delay profile creating section, a Fourier converting section, a pilot signal extracting section, a transmission path characteristic estimating section, an inverse Fourier converting section, and a window control section. In this case, the window control section creates a delay profile for defining a calculation range by leaving a path which exists at a same position in both the delay profiles created by the delay profile creating section and the inverse Fourier converting section and the number of times of detection which is equal to or higher than a threshold value and defines a higher threshold value for the path at a predetermined position from the position of the main path within the delay profile created by the inverse Fourier converting section than for the paths at the other positions.
摘要翻译：正交频分复用（OFDM）解调装置包括延迟分布创建部分，傅里叶变换部分，导频信号提取部分，传输路径特性估计部分，傅里叶逆变换部分和窗口控制部分。在这种情况下，窗口控制部分通过在由延迟分布创建部分和逆傅里叶变换部分创建的两个延迟分布中的相同位置处留下一条路径和次数来创建用于定义计算范围的延迟分布检测值等于或高于阈值，并且在从由傅立叶逆变换部分创建的延迟分布内的主路径的位置处的预定位置处的路径定义更高的阈值，而不是在另一个路径职位

2. 发明授权

US07701841B2 OFDM demodulating apparatus and method 失效
标题翻译： OFDM解调装置及方法
公开(公告)号：US07701841B2
公开(公告)日：2010-04-20
申请号：US11489161
申请日：2006-07-19
申请人： Hidetoshi Kawauchi , Toshihisa Hyakudai , Takuya Okamoto , Atsushi Yajima , Taku Yamagata , Kazutaka Yamamoto , Shigenari Kawabata
发明人： Hidetoshi Kawauchi , Toshihisa Hyakudai , Takuya Okamoto , Atsushi Yajima , Taku Yamagata , Kazutaka Yamamoto , Shigenari Kawabata
IPC分类号： H04J11/00
CPC分类号： H04L25/0232 , H04L27/261 , H04L27/265 , H04L27/2662 , H04L27/2665
摘要： An orthogonal frequency division multiplexing (OFDM) demodulating apparatus includes a delay profile creating section, a Fourier converting section, a pilot signal extracting section, a transmission path characteristic estimating section, an inverse Fourier converting section, and a window control section. In this case, the window control section creates a delay profile for defining a calculation range by leaving a path which exists at a same position in both the delay profiles created by the delay profile creating section and the inverse Fourier converting section and the number of times of detection which is equal to or higher than a threshold value and defines a higher threshold value for the path at a predetermined position from the position of the main path within the delay profile created by the inverse Fourier converting section than for the paths at the other positions.
摘要翻译：正交频分复用（OFDM）解调装置包括延迟分布创建部分，傅里叶变换部分，导频信号提取部分，传输路径特性估计部分，傅里叶逆变换部分和窗口控制部分。在这种情况下，窗口控制部分通过在由延迟分布形成部分和逆傅里叶变换部分创建的两个延迟分布中的相同位置处留下一条路径和次数来创建用于定义计算范围的延迟分布检测值等于或高于阈值，并且在由傅里叶逆变换部分创建的延迟分布内的主路径的位置处的预定位置处的路径定义更高的阈值，而不是在另一个路径职位

3. 发明授权

US07889802B2 Demodulating device, method and program 有权
标题翻译：解调设备，方法和程序
公开(公告)号：US07889802B2
公开(公告)日：2011-02-15
申请号：US11908874
申请日：2007-02-06
申请人： Taku Yamagata , Toshihisa Hyakudai , Shigenari Kawabata
发明人： Taku Yamagata , Toshihisa Hyakudai , Shigenari Kawabata
IPC分类号： H04L27/28
CPC分类号： H04N5/455 , H04L27/22 , H04L27/2647 , H04L27/38 , H04N5/211 , H04N21/4382
摘要： A demodulator includes a complex conjugate signal generator to generate a complex conjugate signal of an OFDM time domain signal (complex signal including an I channel signal and Q channel signal) supplied from an orthogonal demodulation circuit, a delaying unit to delay, by an integral multiple of a predetermined period 1H or 2H, the complex conjugate signal supplied from the complex conjugate signal generator, a complex multiplier to make complex multiplication on the basis of the complex signal generated by the orthogonal demodulation circuit and complex conjugate signal delayed by the integral multiple of the predetermined period by the delay unit, and a determining unit to determine whether an interference wave is included in the modulated signal by making a comparison between the complex multiplication value resulted from the complex multiplication made by the complex multiplier and an arbitrary threshold.
摘要翻译：解调器包括复共轭信号发生器，用于产生从正交解调电路提供的OFDM时域信号（包括I信道信号和Q信道信号的复信号）的复共轭信号，延迟单元以整数倍从复共轭信号发生器提供的复共轭信号，复数乘法器，根据由正交解调电路产生的复信号和复数共轭信号进行复乘以延迟整数倍的整数倍所述延迟单元的所述预定周期，以及确定单元，通过对由所述复数乘法器产生的复乘产生的复数乘法值与任意阈值进行比较，来确定所述调制信号中是否包含干扰波。

4. 发明申请

US20080192844A1 Demodulating Device, Method and Program 有权
标题翻译：解调装置，方法和程序
公开(公告)号：US20080192844A1
公开(公告)日：2008-08-14
申请号：US11908874
申请日：2007-02-06
申请人： Taku Yamagata , Toshihisa Hyakudai , Shigenari Kawabata
发明人： Taku Yamagata , Toshihisa Hyakudai , Shigenari Kawabata
IPC分类号： H04L27/28
CPC分类号： H04N5/455 , H04L27/22 , H04L27/2647 , H04L27/38 , H04N5/211 , H04N21/4382
摘要： A demodulator includes a complex conjugate signal generator to generate a complex conjugate signal of an OFDM time domain signal (complex signal including an I channel signal and Q channel signal) supplied from an orthogonal demodulation circuit, a delaying unit to delay, by an integral multiple of a predetermined period 1H or 2H, the complex conjugate signal supplied from the complex conjugate signal generator, a complex multiplier to make complex multiplication on the basis of the complex signal generated by the orthogonal demodulation circuit and complex conjugate signal delayed by the integral multiple of the predetermined period by the delay unit, and a determining unit to determine whether an interference wave is included in the modulated signal by making a comparison between the complex multiplication value resulted from the complex multiplication made by the complex multiplier and an arbitrary threshold.
摘要翻译：解调器包括复共轭信号发生器，用于产生从正交解调电路提供的OFDM时域信号（包括I信道信号和Q信道信号的复信号）的复共轭信号，延迟单元以整数倍从复共轭信号发生器提供的复共轭信号，复数乘法器，根据由正交解调电路产生的复信号和复数共轭信号进行复乘以延迟整数倍的整数倍所述延迟单元的所述预定周期，以及确定单元，通过对由所述复数乘法器产生的复乘产生的复数乘法值与任意阈值进行比较，来确定所述调制信号中是否包含干扰波。

5. 发明授权

US07284145B2 Clock control circuit and integrated circuit 失效
标题翻译：时钟控制电路和集成电路
公开(公告)号：US07284145B2
公开(公告)日：2007-10-16
申请号：US10909910
申请日：2004-08-02
申请人： Shigenari Kawabata
发明人： Shigenari Kawabata
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the target circuit changes from a disabled state to enabled state, the supply of the clock signal to the target circuit starts in accordance with the system clock signal, and if a valid output instruction signal indicating timings of data output from the target circuit changes from the enabled state to disabled state, the supply of the clock signal is stopped after a lapse of a predetermined time period set externally. The clock control circuit for supplying the valid clock to the target circuit can therefore be used in common for a variety of waveforms of a valid input flag and a valid output flag.
摘要翻译：本发明的时钟管理控制电路是用于根据系统时钟信号将有效的时钟信号提供给目标电路的时钟控制电路。当指示输入到目标电路的数据的定时的有效输入指令信号从禁止状态改变为使能状态时，根据系统时钟信号向目标电路提供时钟信号，并且如果有效的输出指令信号指示从目标电路输出的数据的定时从使能状态变为禁止状态时，在经外部设定的预定时间段之后停止提供时钟信号。因此，用于向目标电路提供有效时钟的时钟控制电路可以用于有效输入标志和有效输出标志的各种波形。

6. 发明申请

US20050030077A1 Clock control circuit and integrated circuit 失效
标题翻译：时钟控制电路和集成电路
公开(公告)号：US20050030077A1
公开(公告)日：2005-02-10
申请号：US10909910
申请日：2004-08-02
申请人： Shigenari Kawabata
发明人： Shigenari Kawabata
IPC分类号： G06F1/04 , G06F1/32 , H03K5/01
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the target circuit changes from a disabled state to enabled state, the supply of the clock signal to the target circuit starts in accordance with the system clock signal, and if a valid output instruction signal indicating timings of data output from the target circuit changes from the enabled state to disabled state, the supply of the clock signal is stopped after a lapse of a predetermined time period set externally. The clock control circuit for supplying the valid clock to the target circuit can therefore be used in common for a variety of waveforms of a valid input flag and a valid output flag.
摘要翻译：本发明的时钟管理控制电路是用于根据系统时钟信号将有效的时钟信号提供给目标电路的时钟控制电路。当指示输入到目标电路的数据的定时的有效输入指令信号从禁止状态改变为使能状态时，根据系统时钟信号向目标电路提供时钟信号，并且如果有效的输出指令信号指示从目标电路输出的数据的定时从使能状态变为禁止状态时，在经外部设定的预定时间段之后停止提供时钟信号。因此，用于向目标电路提供有效时钟的时钟控制电路可以用于有效输入标志和有效输出标志的各种波形。

7. 发明申请

US20080028257A1 Clock control circuit and integrated circuit 审中-公开
标题翻译：时钟控制电路和集成电路
公开(公告)号：US20080028257A1
公开(公告)日：2008-01-31
申请号：US11903104
申请日：2007-09-20
申请人： Shigenari Kawabata
发明人： Shigenari Kawabata
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the target circuit changes from a disabled state to enabled state, the supply of the clock signal to the target circuit starts in accordance with the system clock signal, and if a valid output instruction signal indicating timings of data output from the target circuit changes from the enabled state to disabled state, the supply of the clock signal is stopped after a lapse of a predetermined time period set externally. The clock control circuit for supplying the valid clock to the target circuit can therefore be used in common for a variety of waveforms of a valid input flag and a valid output flag.
摘要翻译：本发明的时钟管理控制电路是用于根据系统时钟信号将有效的时钟信号提供给目标电路的时钟控制电路。当指示输入到目标电路的数据的定时的有效输入指令信号从禁止状态改变为使能状态时，根据系统时钟信号向目标电路提供时钟信号，并且如果有效的输出指令信号指示从目标电路输出的数据的定时从使能状态变为禁止状态时，在经外部设定的预定时间段之后停止提供时钟信号。因此，用于向目标电路提供有效时钟的时钟控制电路可以用于有效输入标志和有效输出标志的各种波形。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式