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1. 发明授权

US08207026B2 Manufacturing method of thin film transistor and manufacturing method of display device 有权
标题翻译：薄膜晶体管的制造方法及显示装置的制造方法
公开(公告)号：US08207026B2
公开(公告)日：2012-06-26
申请号：US12693037
申请日：2010-01-25
申请人： Hideomi Suzawa , Takafumi Mizoguchi , Koji Dairiki , Mayumi Mikami , Yumiko Saito
发明人： Hideomi Suzawa , Takafumi Mizoguchi , Koji Dairiki , Mayumi Mikami , Yumiko Saito
IPC分类号： H01L21/764
CPC分类号： H01L27/1288 , H01L27/1214
摘要： To provide a method for manufacturing a thin film transistor and a display device using a small number of masks, a thin film transistor is manufactured in such a manner that a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked; then, a resist mask is formed thereover; first etching is performed to form a thin-film stack body; second etching in which the first conductive film is side-etched is performed by dry-etching to form a gate electrode layer; and a source electrode, a drain electrode, and the like are formed. Before the dry etching, it is preferred that at least a side surface of the etched semiconductor film be oxidized.
摘要翻译：为了提供制造薄膜晶体管的方法和使用少量掩模的显示装置，制造薄膜晶体管，使得第一导电膜，绝缘膜，半导体膜，杂质半导体膜，并且第二导电膜被堆叠; 然后在其上形成抗蚀剂掩模; 执行第一蚀刻以形成薄膜堆叠体; 通过干蚀刻进行第一导电膜被侧蚀刻的第二蚀刻，以形成栅电极层; 并且形成源电极，漏电极等。在干蚀刻之前，优选地，蚀刻的半导体膜的至少一个侧表面被氧化。

2. 发明授权

US08035107B2 Method for manufacturing display device 有权
标题翻译：显示装置制造方法
公开(公告)号：US08035107B2
公开(公告)日：2011-10-11
申请号：US12368759
申请日：2009-02-10
申请人： Takafumi Mizoguchi , Mayumi Mikami , Yumiko Saito
发明人： Takafumi Mizoguchi , Mayumi Mikami , Yumiko Saito
IPC分类号： H01L29/786
CPC分类号： H01L21/764 , H01L27/1288
摘要： A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, a second conductive film, and a first resist mask are formed; first etching is performed to expose at least a surface of the first conductive film; second etching accompanied by side etching is performed on part of the first conductive film to form a gate electrode layer; a second resist mask is formed; third etching is performed to form a source and drain electrode layers, a source and drain regions, and a semiconductor layer; a second insulating film is formed; an opening portion is formed in the second insulating film to partially expose the source or drain electrode layer; a pixel electrode is selectively formed in the opening portion and over the second insulating film; and a supporting portion formed using the gate electrode layer is formed in a region overlapping with the opening portion.
摘要翻译：形成第一导电膜，第一绝缘膜，半导体膜，杂质半导体膜，第二导电膜和第一抗蚀剂掩模; 执行第一蚀刻以暴露第一导电膜的至少一个表面; 在第一导电膜的一部分上进行伴随着侧蚀刻的第二蚀刻，以形成栅电极层; 形成第二抗蚀剂掩模; 执行第三蚀刻以形成源极和漏极电极层，源极和漏极区域以及半导体层; 形成第二绝缘膜; 在第二绝缘膜中形成开口部分以部分地暴露源极或漏极电极层; 在开口部分和第二绝缘膜上选择性地形成像素电极; 并且在与开口部重叠的区域中形成使用该栅电极层形成的支撑部。

3. 发明授权

US08901561B2 Method for manufacturing display device 有权
标题翻译：显示装置制造方法
公开(公告)号：US08901561B2
公开(公告)日：2014-12-02
申请号：US13238019
申请日：2011-09-21
申请人： Takafumi Mizoguchi , Mayumi Mikami , Yumiko Saito
发明人： Takafumi Mizoguchi , Mayumi Mikami , Yumiko Saito
IPC分类号： H01L33/08 , H01L27/12 , H01L21/764
CPC分类号： H01L21/764 , H01L27/1288
摘要： A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, a second conductive film, and a first resist mask are formed; first etching is performed to expose at least a surface of the first conductive film; second etching accompanied by side etching is performed on part of the first conductive film to form a gate electrode layer; a second resist mask is formed; third etching is performed to form a source and drain electrode layers, a source and drain regions, and a semiconductor layer; a second insulating film is formed; an opening portion is formed in the second insulating film to partially expose the source or drain electrode layer; a pixel electrode is selectively formed in the opening portion and over the second insulating film; and a supporting portion formed using the gate electrode layer is formed in a region overlapping with the opening portion.
摘要翻译：形成第一导电膜，第一绝缘膜，半导体膜，杂质半导体膜，第二导电膜和第一抗蚀剂掩模; 执行第一蚀刻以暴露第一导电膜的至少一个表面; 在第一导电膜的一部分上进行伴随着侧蚀刻的第二蚀刻，以形成栅电极层; 形成第二抗蚀剂掩模; 执行第三蚀刻以形成源极和漏极电极层，源极和漏极区域以及半导体层; 形成第二绝缘膜; 在第二绝缘膜中形成开口部分以部分地暴露源极或漏极电极层; 在开口部分和第二绝缘膜上选择性地形成像素电极; 并且在与开口部重叠的区域中形成使用该栅电极层形成的支撑部。

4. 发明申请

US20090212296A1 METHOD FOR MANUFACTURING DISPLAY DEVICE 有权
标题翻译：制造显示装置的方法
公开(公告)号：US20090212296A1
公开(公告)日：2009-08-27
申请号：US12368759
申请日：2009-02-10
申请人： Takafumi Mizoguchi , Mayumi Mikami , Yumiko Saito
发明人： Takafumi Mizoguchi , Mayumi Mikami , Yumiko Saito
IPC分类号： H01L29/786 , H01L33/00
CPC分类号： H01L21/764 , H01L27/1288
摘要： A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, a second conductive film, and a first resist mask are formed; first etching is performed to expose at least a surface of the first conductive film; second etching accompanied by side etching is performed on part of the first conductive film to form a gate electrode layer; a second resist mask is formed; third etching is performed to form a source and drain electrode layers, a source and drain regions, and a semiconductor layer; a second insulating film is formed; an opening portion is formed in the second insulating film to partially expose the source or drain electrode layer; a pixel electrode is selectively formed in the opening portion and over the second insulating film; and a supporting portion formed using the gate electrode layer is formed in a region overlapping with the opening portion.
摘要翻译：形成第一导电膜，第一绝缘膜，半导体膜，杂质半导体膜，第二导电膜和第一抗蚀剂掩模; 执行第一蚀刻以暴露第一导电膜的至少一个表面; 在第一导电膜的一部分上进行伴随着侧蚀刻的第二蚀刻，以形成栅电极层; 形成第二抗蚀剂掩模; 执行第三蚀刻以形成源极和漏极电极层，源极和漏极区域以及半导体层; 形成第二绝缘膜; 在第二绝缘膜中形成开口部分以部分地暴露源极或漏极电极层; 在开口部分和第二绝缘膜上选择性地形成像素电极; 并且在与开口部重叠的区域中形成使用该栅电极层形成的支撑部。

5. 发明授权

US08436403B2 Semiconductor device including transistor provided with sidewall and electronic appliance 有权
标题翻译：包括设置有侧壁和电子设备的晶体管的半导体器件
公开(公告)号：US08436403B2
公开(公告)日：2013-05-07
申请号：US13014081
申请日：2011-01-26
申请人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
发明人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L21/84
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/45 , H01L29/66969 , Y10T428/24421
摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.
摘要翻译：一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

6. 发明授权

US08501564B2 Semiconductor element, semiconductor device, and method for manufacturing the same 有权
公开(公告)号：US08501564B2
公开(公告)日：2013-08-06
申请号：US12956624
申请日：2010-11-30
申请人： Hideomi Suzawa , Motomu Kurata , Mayumi Mikami
发明人： Hideomi Suzawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/7869 , H01L27/108 , H01L27/1225 , H01L29/12 , H01L29/41733 , H01L29/42384 , H01L29/66969 , H01L29/78648 , H01L29/78696 , H01L2029/42388
摘要： The semiconductor element includes an oxide semiconductor layer on an insulating surface; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer. The source electrode layer and the drain electrode layer have sidewalls which are in contact with a top surface of the oxide semiconductor layer.

7. 发明申请

US20110133177A1 Semiconductor Element, Semiconductor Device, And Method For Manufacturing The Same 有权
标题翻译：半导体元件，半导体器件及其制造方法
公开(公告)号：US20110133177A1
公开(公告)日：2011-06-09
申请号：US12956624
申请日：2010-11-30
申请人： Hideomi Suzawa , Motomu Kurata , Mayumi Mikami
发明人： Hideomi Suzawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L29/786 , H01L21/336 , H01L21/44
CPC分类号： H01L29/7869 , H01L27/108 , H01L27/1225 , H01L29/12 , H01L29/41733 , H01L29/42384 , H01L29/66969 , H01L29/78648 , H01L29/78696 , H01L2029/42388
摘要： The semiconductor element includes an oxide semiconductor layer on an insulating surface; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer. The source electrode layer and the drain electrode layer have sidewalls which are in contact with a top surface of the oxide semiconductor layer.
摘要翻译：半导体元件在绝缘表面上包括氧化物半导体层; 氧化物半导体层上的源电极层和漏电极层; 氧化物半导体层上的栅极绝缘层，源极电极层和漏极电极层; 以及栅极绝缘层上的栅极电极层。源电极层和漏电极层具有与氧化物半导体层的顶表面接触的侧壁。

8. 发明授权

US08492840B2 Semiconductor device having an oxide semiconductor layer 有权
标题翻译：具有氧化物半导体层的半导体器件
公开(公告)号：US08492840B2
公开(公告)日：2013-07-23
申请号：US13008285
申请日：2011-01-18
申请人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
发明人： Shunpei Yamazaki , Hiromichi Godo , Hideomi Suzawa , Shinya Sasagawa , Motomu Kurata , Mayumi Mikami
IPC分类号： H01L27/12
CPC分类号： H01L29/7869
摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.
摘要翻译：本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层，其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

9. 发明申请

US20130224581A1 NEGATIVE ELECTRODE OF POWER STORAGE DEVICE AND POWER STORAGE DEVICE 审中-公开
标题翻译：蓄电装置和蓄电装置的负极
公开(公告)号：US20130224581A1
公开(公告)日：2013-08-29
申请号：US13597675
申请日：2012-08-29
申请人： Yumiko SAITO , Rie Yokoi , Mayumi Mikami
发明人： Yumiko SAITO , Rie Yokoi , Mayumi Mikami
IPC分类号： H01M4/38 , H01G11/50
CPC分类号： H01G11/48 , H01G11/30 , H01G11/32 , H01G11/50 , H01G11/52 , H01G11/62 , H01M4/0404 , H01M4/0471 , H01M4/13 , H01M4/131 , H01M4/137 , H01M4/1391 , H01M4/1399 , H01M4/366 , H01M4/386 , H01M4/387 , H01M4/483 , H01M4/606 , H01M4/662 , H01M10/0525 , H01M2004/027 , H01M2220/30 , Y02E60/13 , Y02T10/7022
摘要： A mixture of amorphous PAHs and at least one of a carrier ion storage metal, a Sn compound, a carrier ion storage alloy, a metal compound, Si, Sb, and SiO2 is used as the negative electrode active material. The theoretical capacity of amorphous PAHs greatly exceeds that of a graphite-based carbon material. Thus, the use of amorphous PAHs enables the negative electrode active material to have a higher capacity than in the case of using the graphite-based carbon material. Further, addition of at least one of the carrier ion storage metal, the Sn compound, the carrier ion storage alloy, the metal compound, Si, Sb, and SiO2 to the amorphous PAHs enables the negative electrode active material to have a higher capacity than the case of only using the amorphous PAHs.
摘要翻译：使用无定形PAH和载流子离子存储金属，Sn化合物，载流子离子储存合金，金属化合物，Si，Sb和SiO 2中的至少一种的混合物作为负极活性物质。无定形多环芳烃的理论能力大大超过石墨基碳材料的理论能力。因此，使用无定形PAH使得负极活性物质比使用石墨基碳材料的情况下具有更高的容量。此外，向非晶PAH中添加载体离子存储金属，Sn化合物，载体离子保存合金，金属化合物，Si，Sb和SiO 2中的至少一种使负极活性物质的容量比仅使用无定形多环芳烃的情况。

10. 发明授权

US08865270B2 Method for manufacturing power storage device 有权
标题翻译：蓄电装置的制造方法
公开(公告)号：US08865270B2
公开(公告)日：2014-10-21
申请号：US13339486
申请日：2011-12-29
申请人： Mayumi Mikami , Takuya Miwa , Kuniharu Nomoto , Takeshi Osada
发明人： Mayumi Mikami , Takuya Miwa , Kuniharu Nomoto , Takeshi Osada
IPC分类号： B05D5/00 , B05D5/12 , H01M4/1397 , H01M4/36 , H01M4/58
CPC分类号： H01M4/1397 , H01M4/36 , H01M4/366 , H01M4/58 , H01M4/5825 , Y02E60/122 , Y02P70/54 , Y02T10/7011 , Y10T29/49108 , Y10T29/49115
摘要： The power extraction efficiency of a nonaqueous electrolyte secondary battery such as a lithium ion battery is improved. A material having magnetic susceptibility anisotropy such as an olivine type oxide including a transition metal element is used for active material particles. The active material particles and an electrolyte solution are mixed to form a slurry. The slurry is applied to a current collector, and then the current collector is left in a magnetic field. Thus, the active material particles are oriented. With the use of active material particles oriented in such a manner, the power extraction efficiency can be improved.
摘要翻译：提高锂离子电池等非水电解质二次电池的功率提取效率。使用具有磁化率各向异性的材料，例如包含过渡金属元素的橄榄石型氧化物作为活性物质颗粒。将活性物质粒子和电解液混合形成浆料。将浆料施加到集电体上，然后将集电体置于磁场中。因此，活性物质颗粒被取向。通过使用以这种方式取向的活性材料颗粒，可以提高功率提取效率。

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