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1. 发明授权

US4905314A Semiconductor integrated circuit device having an object circuit to which output voltages of the sub- and main booster circuits are applied 失效
标题翻译：半导体集成电路装置具有对主电路施加副主电路和主升压电路的输出电压的目标电路
公开(公告)号：US4905314A
公开(公告)日：1990-02-27
申请号：US184580
申请日：1988-04-21
申请人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
发明人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H02M3/07 , H03K3/356 , H03K17/06
CPC分类号： G11C5/145 , G11C16/30 , H03K17/06 , H03K3/356008
摘要： A sub-booster circuit for further stepping up an output voltage of a main booster circuit includes a first MOS transistor having a drain connected to the output terminal of the main booster circuit, and a gate connected to an input terminal of an object circuit, a second MOS transistor having a drain and a gate connected to the source of the first MOS transistor and a source connected to the input terminal of the object circuit, and a MOS capacitor having a first electrode connected to a connection node between the first and second MOS transistors and a second electrode connected to receive a clock pulse signal. A threshold voltage of the second MOS transistor is set to be larger in its absolute value than a threshold voltage of the first MOS transistor and the MOS capacitor has substantially the same threshold voltage as that of the second MOS transistor.

2. 发明授权

US4804929A Control pulse generator 失效
标题翻译：控制脉冲发生器
公开(公告)号：US4804929A
公开(公告)日：1989-02-14
申请号：US101667
申请日：1987-09-28
申请人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
发明人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
IPC分类号： H03K3/037 , H03K17/22 , H03L1/00 , H03B1/00
CPC分类号： H03K17/223
摘要： A control pulse generator according to the present invention includes a voltage generator for generating an output voltage proportional to a power supply voltage, an inverter for generating an inversion signal whose signal level is inverted when the output voltage from the voltage generator reaches a predetermined value, and a pulse signal generator for delaying a level inversion timing of the inversion signal by a predetermined delay time, and generating a control pulse having a width corresponding to the delay time. According to the control pulse generator with the above arrangement, the width of the control pulse can be determined on the basis of the delay time of the pulse signal generator, regardless of rise states of the power supply voltage. In addition, the height of the control pulse can be set at a desired value according to a supply voltage to the pulse signal generator, regardless of rise states of the supply voltage.
摘要翻译：根据本发明的控制脉冲发生器包括用于产生与电源电压成比例的输出电压的电压发生器，用于产生当来自电压发生器的输出电压达到预定值时信号电平反转的反相信号的反相器，以及脉冲信号发生器，用于将反转信号的电平反转定时延迟预定的延迟时间，并产生具有对应于延迟时间的宽度的控制脉冲。根据具有上述配置的控制脉冲发生器，无论电源电压的上升状态如何，可以基于脉冲信号发生器的延迟时间来确定控制脉冲的宽度。此外，无论电源电压的上升状态如何，控制脉冲的高度可以根据与脉冲信号发生器的电源电压设定在期望值。

3. 发明授权

US4794562A Electrically-erasable/programmable nonvolatile semiconductor memory device 失效
标题翻译：电可擦除/可编程非易失性半导体存储器件
公开(公告)号：US4794562A
公开(公告)日：1988-12-27
申请号：US94458
申请日：1987-09-09
申请人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
发明人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： H01L29/7883 , H01L27/115
摘要： In an electrically-erasable/programmable nonvolatile semiconductor memory device according to the invention, a one-bit memory cell is constituted by a series circuit of a selecting MOS transistor and a data storage MOS transistor. A floating gate electrode and a control gate electrode are formed in the data storage MOS transistor, One portion of the floating gate electrode is formed on a channel region of the data storage MOS transistor through a gate insulating film. The other portion of the floating gate electrode is formed on a drain region of the data storage MOS transistor through a gate insulating film, a portion of which is sufficiently thinner than the gate insulating film. One and the other portions of the floating gate electrode are structurally separated from each other but are electrically connected with each other on a field region. A control gate electrode having substantially the same shape as that of the floating gate electrode is formed thereon through a gate insulating film.
摘要翻译：在根据本发明的电可擦除/可编程非易失性半导体存储器件中，一位存储单元由选择MOS晶体管和数据存储MOS晶体管的串联电路构成。在数据存储MOS晶体管中形成浮栅电极和控制栅极，通过栅极绝缘膜在浮动栅极的一部分形成在数据存储MOS晶体管的沟道区上。浮置栅电极的另一部分通过栅极绝缘膜形成在数据存储MOS晶体管的漏极区上，栅极绝缘膜的一部分比栅极绝缘膜充分薄。浮栅电极的一个和另外部分在结构上彼此分离，但是在场区域上彼此电连接。通过栅极绝缘膜在其上形成具有与浮栅电极基本相同形状的控制栅电极。

4. 发明授权

US4692834A Electrostatic discharge protection circuit with variable limiting threshold for MOS device 失效
标题翻译： MOS器件具有可变限流阈值的静电放电保护电路
公开(公告)号：US4692834A
公开(公告)日：1987-09-08
申请号：US761707
申请日：1985-08-02
申请人： Hiroshi Iwahashi , Masamichi Asano , Akira Narita
发明人： Hiroshi Iwahashi , Masamichi Asano , Akira Narita
IPC分类号： H01L27/06 , H02H9/04 , H02H3/20
CPC分类号： H02H9/046
摘要： An electrostatic discharge protection circuit is provided with a variable threshold for limiting the potential of an input signal having a given high or low voltage, and is adapted to an EPROM containing an input MOS transistor which is responsive to the input signal. The protection circuit is associated with an input terminal for receiving the input signal. The input terminal is coupled to the gate of the input MOS transistor. The protection circuit also includes a circuit element for limiting or suppressing the input signal potential at the variable threshold. The gate of the input MOS transistor receives the potential limited signal from the circuit element. The circuit element is responsive to a given threshold control potential. The variable threshold is enhanced by the given threshold control potential when a high-voltage input signal is applied to the input terminal.
摘要翻译：静电放电保护电路具有用于限制具有给定高或低电压的输入信号的电位的可变阈值，并且适用于包含响应于输入信号的输入MOS晶体管的EPROM。保护电路与用于接收输入信号的输入端相关联。输入端耦合到输入MOS晶体管的栅极。保护电路还包括用于限制或抑制在可变阈值处的输入信号电位的电路元件。输入MOS晶体管的栅极接收来自电路元件的电位限制信号。电路元件响应给定的阈值控制电位。当将高电压输入信号施加到输入端时，通过给定的阈值控制电位增强可变阈值。

5. 发明授权

US4697101A Read/write control circuit 失效
标题翻译：读/写控制电路
公开(公告)号：US4697101A
公开(公告)日：1987-09-29
申请号：US645392
申请日：1984-08-29
申请人： Hiroshi Iwahashi , Masamichi Asano , Masaki Momodomi , Hidenobu Minagawa , Kazuto Suzuki , Akira Narita
发明人： Hiroshi Iwahashi , Masamichi Asano , Masaki Momodomi , Hidenobu Minagawa , Kazuto Suzuki , Akira Narita
IPC分类号： G11C16/12 , G11C16/30 , H03K19/096 , G06F7/38 , H03K17/16
CPC分类号： G11C16/30 , G11C16/12
摘要： A semiconductor integrated circuit which has a CMOS inverter formed of p- and n-channel MOSFETs, and a D-type n-channel MOSFET coupled at the gate to the output terminal of the CMOS inverter, having one end coupled to a high voltage terminal and the other end coupled to the drain of the p-channel MOSFET.
摘要翻译：一种半导体集成电路，其具有由p-沟道MOSFET和n沟道MOSFET形成的CMOS反相器，以及在栅极处连接到CMOS反相器的输出端的D型n沟道MOSFET，其一端耦合到高电压端子另一端耦合到p沟道MOSFET的漏极。

6. 发明授权

US4979146A Electrically erasable non-volatile semiconductor device 失效
标题翻译：电可擦除非易失性半导体器件
公开(公告)号：US4979146A
公开(公告)日：1990-12-18
申请号：US302712
申请日：1989-01-27
申请人： Sadayuki Yokoyama , Masamichi Asano , Hiroshi Iwahashi , Kaoru Nakagawa
发明人： Sadayuki Yokoyama , Masamichi Asano , Hiroshi Iwahashi , Kaoru Nakagawa
IPC分类号： G11C17/00 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/16 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/112 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/08 , G11C16/12 , G11C16/16 , H01L2924/0002
摘要： In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells are arranged in a matrix form and are connected to corresponding ones of row and column lines. In a data writing mode, a first voltage Vp at is applied to the column lines so that the drains of the memory cells are maintained at a drain potential, and a second voltage is applied to the row lines so that a sum level of the drain potential and the threshold voltage of the memory cell is not smaller than the floating gate potential of the memory cell.

7. 发明授权

US4916334A High voltage booster circuit for use in EEPROMs 失效
标题翻译：用于EEPROM的高压升压电路
公开(公告)号：US4916334A
公开(公告)日：1990-04-10
申请号：US226312
申请日：1988-07-29
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C16/30 , H02M3/07 , H03K5/02
CPC分类号： G11C16/30 , H02M3/07 , H03K5/023
摘要： A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.
摘要翻译：半导体集成电路包括以第一电压电平工作的CMOS电路，以将其输出节点设置为第一电压电平或参考电压的电压; 输出电路，用于控制向信号输出节点提供高于第一电压电平的第二电压电平的电压; 以及隔离MOS晶体管，其具有连接在CMOS电路的输出节点和信号输出节点之间的电流路径以及连接以接收控制信号的栅极。 CMOS电路的输出节点被设定为参考电压，其中隔离MOS晶体管的导通电阻保持高电平，其中第二电压电平的电压被保持提供给信号输出节点。此后，隔离MOS晶体管的导通电阻响应于控制信号而减小。

8. 发明授权

US4509148A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4509148A
公开(公告)日：1985-04-02
申请号：US493605
申请日：1983-05-11
申请人： Masamichi Asano , Hiroshi Iwahashi
发明人： Masamichi Asano , Hiroshi Iwahashi
IPC分类号： G11C8/10 , G11C11/4076 , G11C11/408 , G11C17/12 , G11C11/40
CPC分类号： G11C17/12 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C8/10
摘要： A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of said row decoders for controlling the conduction state of the switching MOS transistors.
摘要翻译：半导体存储器电路包括多个半导体存储区域，连接到存储区域的多个数据线，用于相对于其传输数据;多条字线，用于将存取信号发送到存储区域;列解码器，连接到所述多条数据线和行解码器具有分别连接到存储区域的解码部分和连接在解码器部分与电压供应端子之间的开关式MOS晶体管。存储电路还包括连接到所述行解码器的开关MOS晶体管的存储器选择电路，用于控制开关MOS晶体管的导通状态。

9. 发明授权

US4447895A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4447895A
公开(公告)日：1984-05-08
申请号：US192203
申请日：1980-09-30
申请人： Masamichi Asano , Hiroshi Iwahashi
发明人： Masamichi Asano , Hiroshi Iwahashi
IPC分类号： G11C8/10 , G11C11/4076 , G11C11/408 , G11C17/12 , G11C11/40
CPC分类号： G11C17/12 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C8/10
摘要： A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of the row decoders for controlling the conduction state of the switching MOS transistors.
摘要翻译：半导体存储器电路包括多个半导体存储区域，连接到存储区域的多个数据线，用于相对于其传输数据;多条字线，用于将存取信号发送到存储区域;列解码器，连接到所述多条数据线和行解码器具有分别连接到存储区域的解码部分和连接在解码器部分与电压供应端子之间的开关式MOS晶体管。存储电路还包括连接到行解码器的开关MOS晶体管的存储器选择电路，用于控制开关MOS晶体管的导通状态。

10. 发明授权

US5364805A Method of manufacturing an EEPROM having an erasing gate electrode 失效
标题翻译：制造具有擦除栅电极的EEPROM的方法
公开(公告)号：US5364805A
公开(公告)日：1994-11-15
申请号：US726881
申请日：1991-07-08
申请人： Tadayuki Taura , Masamichi Asano , Kazunori Kanebako , Hiroshi Iwahashi
发明人： Tadayuki Taura , Masamichi Asano , Kazunori Kanebako , Hiroshi Iwahashi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11517 , H01L27/115
摘要： A memory cell array is formed of a plurality of nonvolatile memory cell transistors arranged in a matrix form. The patterns of the control gate electrode and the source region of each memory cell transistor are formed in parallel and the pattern of the erasing gate electrode is formed to intersect the source region and control gate electrode patterns. A field oxide film is formed in an intersecting portion between the source region and the erasing gate electrode.
摘要翻译：存储单元阵列由以矩阵形式布置的多个非易失性存储单元晶体管形成。并联地形成每个存储单元晶体管的控制栅电极和源极区的图案，并且形成擦除栅电极的图案以与源区和控制栅电极图相交。在源极区域和擦除栅极电极之间的交叉部分中形成场氧化膜。

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