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1. 发明授权

US07577124B2 Relay apparatus, terminal apparatus and relay method 有权
标题翻译：中继装置，终端装置和中继方法
公开(公告)号：US07577124B2
公开(公告)日：2009-08-18
申请号：US10942122
申请日：2004-09-16
申请人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto , Yoshihito Kawai
发明人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto , Yoshihito Kawai
IPC分类号： H04Q7/24 , H04L12/413
CPC分类号： H04B7/15528 , H04L27/2602
摘要： A relay apparatus, terminal apparatus and relay method for relaying signals with a reduced scale of the apparatus, without temporally switching between transmission and reception and with reduced waste of time when relay is performed at the same frequency on a radio communication network on which bidirectional communication is performed. A radio reception section 202 outputs information signals to a switch 208, outputs relay control signals to a demodulation section 204 after subjecting predetermined radio reception processing. The demodulation section 204 demodulates a relay control signal. A relay control signal processing section 206 decides the possibility of relay of information signals and inquires, when the relay is possible, whether the terminal apparatus on the receiving side can receive this information signal or not. Furthermore, the relay control signal processing section 206 connects a switch 208 during the stored relay time. The switch 208 is connected only the information signals to be relayed are received under the control of a relay control section 2063.
摘要翻译：一种中继装置，终端装置和中继方法，用于在设备的规模缩小的情况下中继信号，而不需要在发送和接收之间进行时间上的切换，并且在双向通信的无线电通信网络上以相同频率执行中继时减少了时间浪费被执行。无线接收部202将信息信号输出到开关208，在经过预定的无线接收处理之后，向解调部204输出中继控制信号。解调部204解调继电器控制信号。继电器控制信号处理部分206确定信息信号的中继的可能性，并且当继电器可能时，询问接收侧的终端装置是否可以接收该信息信号。此外，继电器控制信号处理部206在存储的继电器时间期间连接开关208。在继电器控制部分2063的控制下，开关208只连接待接收的信息信号。

2. 发明申请

US20050058104A1 Relay apparatus, terminal apparatus and relay method 有权
标题翻译：中继装置，终端装置和中继方法
公开(公告)号：US20050058104A1
公开(公告)日：2005-03-17
申请号：US10942122
申请日：2004-09-16
申请人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto , Yoshihito Kawai
发明人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto , Yoshihito Kawai
IPC分类号： H04L5/14 , H04B1/707 , H04B7/015 , H04B7/15 , H04B7/155 , H04B7/26 , H04J11/00 , H04J13/00 , H04L27/26 , H04W16/26 , H04W84/18 , H04B7/216
CPC分类号： H04B7/15528 , H04L27/2602
摘要： A relay apparatus, terminal apparatus and relay method for relaying signals with a reduced scale of the apparatus, without temporally switching between transmission and reception and with reduced waste of time when relay is performed at the same frequency on a radio communication network on which bidirectional communication is performed. A radio reception section 202 outputs information signals to a switch 208, outputs relay control signals to a demodulation section 204 after subjecting predetermined radio reception processing. The demodulation section 204 demodulates a relay control signal. A relay control signal processing section 206 decides the possibility of relay of information signals and inquires, when the relay is possible, whether the terminal apparatus on the receiving side can receive this information signal or not. Furthermore, the relay control signal processing section 206 connects a switch 208 during the stored relay time. The switch 208 is connected only the information signals to be relayed are received under the control of a relay control section 2063.
摘要翻译：一种中继装置，终端装置和中继方法，用于在设备的规模缩小的情况下中继信号，而不需要在发送和接收之间进行时间上的切换，并且在双向通信的无线电通信网络上以相同频率执行中继时减少了时间浪费被执行。无线接收部202将信息信号输出到开关208，在经过预定的无线接收处理之后，向解调部204输出中继控制信号。解调部204解调继电器控制信号。继电器控制信号处理部分206确定信息信号的中继的可能性，并且当继电器可能时，询问接收侧的终端装置是否可以接收该信息信号。此外，继电器控制信号处理部206在存储的继电器时间期间连接开关208。在继电器控制部分2063的控制下，开关208只连接待接收的信息信号。

3. 发明授权

US07966360B2 Finite impulse response filter and digital signal receiving apparatus 有权
标题翻译：有限脉冲响应滤波器和数字信号接收装置
公开(公告)号：US07966360B2
公开(公告)日：2011-06-21
申请号：US11833030
申请日：2007-08-02
申请人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto
发明人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto
IPC分类号： G06F17/10
CPC分类号： H03H17/0657 , H03H17/0223 , H03H17/0229 , H03H17/06 , H03H17/0621 , H03H2218/085
摘要： An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.
摘要翻译： A / D转换部分以符号速率M倍的模拟信号执行过采样，以将模拟信号转换为数字信号。 FIR滤波部分具有两个具有多个延迟元件的延迟元件序列。两个延迟元件序列具有不同的延迟方向，即正向和反向。可以切换延迟方向，并且根据具有这种延迟元件序列的有限脉冲响应列，进行卷积计算。相位确定部确定在判定部中作出判定所使用的相位。决定部分使用在相位确定部分中确定的相位来对滤波信号做出决定以产生位数据。因此，实现了数字信号接收装置，其在不增加过采样数量的情况下确定高精度的相位，并且在具有减小的电路规模的情况下执行快速计算。

4. 发明授权

US07254598B2 Finite impulse response filter and digital signal receiving apparatus 有权
标题翻译：有限脉冲响应滤波器和数字信号接收装置
公开(公告)号：US07254598B2
公开(公告)日：2007-08-07
申请号：US10475090
申请日：2003-03-14
申请人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto
发明人： Hidekuni Yomo , Yoshinori Kunieda , Yuuri Yamamoto
IPC分类号： G06F17/10
CPC分类号： H03H17/0657 , H03H17/0223 , H03H17/0229 , H03H17/06 , H03H17/0621 , H03H2218/085
摘要： An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.
摘要翻译： A / D转换部分对符号率M倍的模拟信号进行过采样，以将模拟信号转换为数字信号。 FIR滤波部分具有两个具有多个延迟元件的延迟元件序列。两个延迟元件序列具有不同的延迟方向，即正向和反向。可以切换延迟方向，并且根据具有这种延迟元件序列的有限脉冲响应列，进行卷积计算。相位确定部确定在判定部中作出判定所使用的相位。决定部分使用在相位确定部分中确定的相位来对滤波信号做出决定以产生位数据。因此，实现了数字信号接收装置，其在不增加过采样数量的情况下确定高精度的相位，并且在具有减小的电路规模的情况下执行快速计算。

5. 发明授权

US5426669A Quadrature demodulator 失效
标题翻译：正交解调器
公开(公告)号：US5426669A
公开(公告)日：1995-06-20
申请号：US077586
申请日：1993-06-17
申请人： Yuuri Yamamoto , Kenichi Takahashi , Hiroshi Ohnishi , Yoshinori Kunieda , Naoki Matsubara
发明人： Yuuri Yamamoto , Kenichi Takahashi , Hiroshi Ohnishi , Yoshinori Kunieda , Naoki Matsubara
IPC分类号： H04L7/033 , H04L27/233 , H03D3/18 , H04L27/06
CPC分类号： H04L7/0334 , H04L27/2332
摘要： A quadrature demodulator includes a device for generating first and second reference signals having a quadrature relation with each other. A first demodulating device serves to compare phases of the first reference signal and an input modulated signal to demodulate the input modulated signal into a first binary baseband signal. A second demodulating device serves to compare phases of the second reference signal and the input modulated signal to demodulate the input modulated signal into a second binary baseband signal having a quadrature relation with the first baseband signal. A first counting device operates to count pulses of a clock signal in response to the first baseband signal. A second counting device operates to count pulses of the clock signal in response to the second baseband signal. An address signal is generated in response to the output signals of the first and second counting devices. Data representative of an absolute phase of the input modulated signal is generated in response to the address signal.
摘要翻译：正交解调器包括用于产生彼此具有正交关系的第一和第二参考信号的装置。第一解调装置用于比较第一参考信号和输入调制信号的相位，以将输入的调制信号解调为第一二进制基带信号。第二解调装置用于比较第二参考信号和输入调制信号的相位，以将输入调制信号解调成与第一基带信号具有正交关系的第二二进制基带信号。第一计数装置用于响应于第一基带信号来计数时钟信号的脉冲。第二计数装置用于响应于第二基带信号对时钟信号的脉冲进行计数。响应于第一和第二计数装置的输出信号产生地址信号。响应于地址信号产生表示输入调制信号的绝对相位的数据。

6. 发明授权

US5550867A Complex angle converter 失效
标题翻译：复角转换器
公开(公告)号：US5550867A
公开(公告)日：1996-08-27
申请号：US417528
申请日：1995-04-06
申请人： Yuuri Yamamoto , Kenichi Takahashi , Hiroshi Ohnishi , Yoshinori Kunieda , Naoki Matsubara
发明人： Yuuri Yamamoto , Kenichi Takahashi , Hiroshi Ohnishi , Yoshinori Kunieda , Naoki Matsubara
IPC分类号： H04L7/033 , H04L27/233 , H04L27/06
CPC分类号： H04L7/0334 , H04L27/2332
摘要： A complex angle converter includes a comparing device. The comparing device operates to derive first difference data representing a difference between predetermined reference data and data represented by a first baseband signal. The comparing device further operates to derive second difference data representing a difference between the predetermined reference data and data represented by a second baseband signal having a quadrature relation with the first baseband signal. The comparing device further operates for comparing absolute values of the first difference data and the second difference data, and for outputting a signal representative of a result of the comparing. The complex angle converter also includes a device serving to group an inversion of a highest bit of the first baseband signal and second highest and lower bits of the second baseband signal into a first set. An additional device serves to group a highest bit of the second baseband signal and second highest and lower bits of the first baseband signal into a second set. A selector operates to select one of the first set and the second set in response to the output signal of the comparing device. A decoder is included for decoding the highest bit of the first baseband signal, the highest bit of the second baseband signal, and the selected one of the first set and the second set into data representing a complex angle.
摘要翻译：复角度转换器包括比较装置。比较装置用于导出表示预定参考数据和由第一基带信号表示的数据之间的差异的第一差分数据。比较装置进一步操作以得出表示预定参考数据与由与第一基带信号具有正交关系的第二基带信号表示的数据之间的差异的第二差分数据。比较装置还用于比较第一差分数据和第二差分数据的绝对值，并输出表示比较结果的信号。复角转换器还包括用于将第一基带信号的最高位和第二基带信号的第二高位和低位的反转分组为第一组的装置。附加设备用于将第二基带信号的最高位和第一基带信号的第二高位和低位分组成第二组。选择器响应于比较装置的输出信号选择第一组和第二组中的一个。包括解码器，用于将第一基带信号的最高位，第二基带信号的最高位和第一组和第二组中选定的一个译码成表示复角的数据。

7. 发明授权

US5555247A Frame synchronizing apparatus for quadrature modulation data communication radio receiver 失效
公开(公告)号：US5555247A
公开(公告)日：1996-09-10
申请号：US515607
申请日：1995-08-16
申请人： Akihiko Matsuoka , Hiroshi Ohnishi , Yoshinori Kunieda , Kouei Misaizu , Yuuri Yamamoto
发明人： Akihiko Matsuoka , Hiroshi Ohnishi , Yoshinori Kunieda , Kouei Misaizu , Yuuri Yamamoto
IPC分类号： H03L7/085 , H04J3/06 , H04L7/033 , H04L7/04 , H04L7/08
CPC分类号： H04L7/042 , H03L7/085 , H04J3/06 , H04L7/0331 , H04L7/08
摘要： In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals. So long as the detected phase differences are successively effectively zero and the cumulative phase error is sufficiently small, the phase of the frame synchronizing signal is held unchanged, thereby achieving a high degree of phase stability.

8. 发明授权

US5703913A Timing signal generator 失效
标题翻译：定时信号发生器
公开(公告)号：US5703913A
公开(公告)日：1997-12-30
申请号：US684442
申请日：1996-07-19
申请人： Yuuri Yamamoto , Kenichi Takahashi , Hiroshi Ohnishi , Yoshinori Kunieda , Naoki Matsubara
发明人： Yuuri Yamamoto , Kenichi Takahashi , Hiroshi Ohnishi , Yoshinori Kunieda , Naoki Matsubara
IPC分类号： H04L7/033 , H04L27/233 , H04L7/00
CPC分类号： H04L7/0334 , H04L27/2332
摘要： A timing signal generator includes a demodulator for an input modulated signal to provide first and second baseband signals having a quadrature relation relative to each other. A converter is used to convert the first and second baseband signals into angle data representing a phase, and a calculator is used to calculate a difference between the phase represented by current angle data and the phase represented by previous angle data, preceding the current angle data by a 1-symbol interval. The calculator outputs data representative of the calculated phase difference. A further converter converts the calculator output data into a binary reference signal responsive to which of predetermined divided regions contains a point corresponding to the calculated difference data. Also included is a generator for generating a symbol timing signal in synchronism with the binary reference signal.
摘要翻译：定时信号发生器包括用于输入调制信号的解调器，以提供具有彼此正交关系的第一和第二基带信号。 A转换器用于将第一和第二基带信号转换成表示相位的角度数据，并且使用计算器来计算当前角度数据所表示的相位与由当前角度数据之前的先前角度数据表示的相位之间的差以1符号间隔。计算器输出表示计算出的相位差的数据。另外的转换器将计算器输出数据转换成二进制参考信号，响应于哪个预定分割区域包含对应于所计算的差分数据的点。还包括用于与二进制参考信号同步地产生符号定时信号的发生器。

9. 发明授权

US5726974A Receiving circuit having a frequency compensated local oscillation circuit 失效
标题翻译：具有频率补偿本地振荡电路的接收电路
公开(公告)号：US5726974A
公开(公告)日：1998-03-10
申请号：US666838
申请日：1996-06-19
申请人： Yoshinori Kunieda , Yuuri Yamamoto , Kenichi Takahashi
发明人： Yoshinori Kunieda , Yuuri Yamamoto , Kenichi Takahashi
IPC分类号： H04J11/00 , H04L27/744
CPC分类号： H04J11/00
摘要： A receiving ckt for receiving a transmitted SIG including FRQ divided carriers, comprises: a FRQ conversion ckt responsive to the LO SIG with a LO for generating a LO SIG with LO FRQ controlled according to a FRQ CONT SIG for FRQ converting the transmitted SIG into an IF SIG; a orthogonal signal separation ckt separating the IF SIG into I and Q components; a complex FFT conversion ckt for complex FFT converting the I and Q components and outputting conversion SIGs to be decoded arranged in FRQ base; an ELEC PWR measurement ckt measuring values of ELEC PWRs of the conversion SIGs; and a prediction ckt for predicting a CTR FRQ of the FRQ divided carriers from a FRQ distribution of the values of ELEC PWRs from the ELEC PWR measurement ckt and generating the FRQ CONT SIG according to the predicted center FRQ. The CTR FRQ may be detected by a REF carrier detection ckt responsive to the complex FFT processing ckt detecting a REF carrier or a carrier pattern included in the transmitted SIG. A correlation between the conversion SIGs and a REF SIG having values varied every predetermined interval within a symbol period is detected to generate the FRQ CONT SIG, wherein a phase compensating ckt for compensating phase of the conversion SIGs in response to the FRQ CONT SIG may be provided.
摘要翻译：用于接收包括FRQ分割载波的发送的SIG的接收端包括：响应于LO SIG的FRQ转换ckt，用于产生具有LO FRQ的LO FR的LO信号，其中LO FRQ根据FRQ CONT SIG进行控制，用于将所发送的SIG转换为 IF SIG; 将IF SIG分成I和Q分量的正交信号分离ckt; 复合FFT转换ckt，用于复合FFT转换I和Q分量，并输出被布置在FRQ基底中的要解码的转换SIG; 测量转换SIG的ELEC PWR值的ELEC PWR测量值; 以及预测ckt，用于根据来自ELEC PWR测量ckt的ELEC PWR的值的FRQ分布来预测FRQ分割载波的CTR FRQ，并根据预测中心FRQ生成FRQ CONT SIG。可以通过响应于检测到发送的SIG中包括的REF载波或载波模式的复FFT处理ckt的REF载波检测ckt来检测CTR FRQ。检测在符号周期内每个预定间隔变化的值的转换SIG与REF SIG之间的相关性，以产生FRQ CONT SIG，其中响应于FRQ CONT SIG而补偿相位变化SIG的相位补偿ckt可以是提供。

10. 发明授权

US5463627A Frame synchronizing apparatus for quadrature modulation data communication radio receiver 失效
标题翻译：正交调制数据通信无线电接收机的帧同步装置
公开(公告)号：US5463627A
公开(公告)日：1995-10-31
申请号：US200592
申请日：1994-02-23
申请人： Akihiko Matsuoka , Hiroshi Ohnishi , Yoshinori Kunieda , Kouei Misaizu , Yuuri Yamamoto
发明人： Akihiko Matsuoka , Hiroshi Ohnishi , Yoshinori Kunieda , Kouei Misaizu , Yuuri Yamamoto
IPC分类号： H03L7/085 , H04J3/06 , H04L7/033 , H04L7/04 , H04L7/08
CPC分类号： H04L7/042 , H03L7/085 , H04J3/06 , H04L7/0331 , H04L7/08
摘要： In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals. So long as the detected phase differences are successively effectively zero and the cumulative phase error is sufficiently small, the phase of the frame synchronizing signal is held unchanged, thereby achieving a high degree of phase stability.
摘要翻译：在数字数据无线电通信系统的接收机装置的帧同步装置中，数据在具有包含每一帧的固定数据序列的帧周期中被发送，数据相关电路获得构成矢量的矢量值之间的向量差的值的连续序列解调的数字基带信号，并且将这些序列与对应于固定数据序列的固定向量差异序列连续地进行比较，以导出基本上不受基带信号中的任何相位旋转影响的相关信号。形成为用于产生帧同步信号的PLL的帧同步电路包括周期性地指示相关信号和帧同步信号之间的检测到的相位差是否为零或正的负相位的相位比较器，以及保持计数值的计数器表示这些信号之间的累积相位误差。只要检测到的相位差连续有效地为零并且累积相位误差足够小，则帧同步信号的相位保持不变，从而实现高度的相位稳定性。

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