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1. 发明公开

CN105684314A 使用FIR滤波器对固定模式抖动的抑制有权
公开(公告)号：CN105684314A
公开(公告)日：2016-06-15
申请号：CN201480037938.9
申请日：2014-07-01
申请人： ESS技术有限公司
发明人：马丁·A·马林森
IPC分类号： H03L7/06
CPC分类号： H03H17/06 , H03H17/0229 , H03H17/0248 , H03H17/0286 , H03H17/0294 , H03H21/0012 , H03H21/002
摘要：公开了用于补偿固定模式抖动的FIR滤波器和构建FIR滤波器的方法。在一个实施方式中，FIR滤波器利用FIR滤波器的系数对具有期望频率分量1的信号进行滤波，该FIR滤波器被选择使得滤波器等效于以下两个组合的FIR滤波器：一个FIR滤波器在滤波器的输出峰频率处具有期望频率；以及第二FIR滤波器，在该第二FIR滤波器中信号被延迟了一段时间，该时间等于期望从输出信号中去除的不同频率的周期的一半。

2. 发明公开

CN1516923A 有限脉冲响应滤波器和数字信号接收装置失效
公开(公告)号：CN1516923A
公开(公告)日：2004-07-28
申请号：CN03800467.4
申请日：2003-03-14
申请人：松下电器产业株式会社
发明人：四方英邦 , 国枝贤德 , 山本裕理
IPC分类号： H03H17/06
CPC分类号： H03H17/0657 , H03H17/0223 , H03H17/0229 , H03H17/06 , H03H17/0621 , H03H2218/085
摘要： A/D转换部件(101)，以符号速率的M倍速率对模拟信号进行重复取样，从而将其转换成数字信号。FIR滤波部件(102)具有两个延迟元件序列，每个延迟元件序列具有多个延迟元件，而且这两个序列具有不同的输入信号延迟方向，即正向和反向。输入信号的延迟方向可被切换，并且根据具有这样的延迟元件序列的有限脉冲响应串进行卷积计算。相位判定部件(103)判定用于在决策部件(104)中做出决策的相位。决策部件(104)使用在相位判定部件(103)中判定的相位对滤波的信号做出决策，并产生位数据。从而获得了一种数字信号接收装置，其以高精确度判定相位而不增加重复取样数，并在进行快速计算的同时具有减小的电路规模。

3. 发明授权

CN102811037B 高效子频带自适应有限脉冲响应滤波有权
公开(公告)号：CN102811037B
公开(公告)日：2015-11-25
申请号：CN201210173585.8
申请日：2012-05-30
申请人：哈曼贝克自动系统股份有限公司
发明人： M.克里斯托夫
IPC分类号： H03H17/02
CPC分类号： H03H17/0266 , H03H17/0229 , H03H21/0012 , H03H2021/0041
摘要：本发明公开了具有至少一个音频通道的音频系统。音频系统包括数字音频处理器，其中对每个通道实施至少一个数字滤波器。每个通道的数字滤波器包括：分析滤波器组，设置成接收宽频带输入音频信号并将输入音频信号划分成多个子频带，从而提供具有相等带宽的子频带信号，子频带信号的频谱组成输入音频信号的频谱；用于每个子频带的子频带FIR滤波器，从而提供各个被滤过的子频带信号；和合成滤波器组，设置成接收被滤过的子频带信号并将子频带信号组合来提供宽频带输出音频信号，其中延迟与每个子频带信号相关联，将子频带信号其中之一的延迟应用到分析滤波器组上游的宽频带输入音频信号并将剩余的延迟应用到分析滤波器组下游的剩余子频带信号。

4. 发明公开

CN102811037A 高效子频带自适应有限脉冲响应滤波有权
公开(公告)号：CN102811037A
公开(公告)日：2012-12-05
申请号：CN201210173585.8
申请日：2012-05-30
申请人：哈曼贝克自动系统股份有限公司
发明人： M.克里斯托夫
IPC分类号： H03H17/02
CPC分类号： H03H17/0266 , H03H17/0229 , H03H21/0012 , H03H2021/0041
摘要：本发明公开了具有至少一个音频通道的音频系统。音频系统包括数字音频处理器，其中对每个通道实施至少一个数字滤波器。每个通道的数字滤波器包括：分析滤波器组，设置成接收宽频带输入音频信号并将输入音频信号划分成多个子频带，从而提供具有相等带宽的子频带信号，子频带信号的频谱组成输入音频信号的频谱；用于每个子频带的子频带FIR滤波器，从而提供各个被滤过的子频带信号；和合成滤波器组，设置成接收被滤过的子频带信号并将子频带信号组合来提供宽频带输出音频信号，其中延迟与每个子频带信号相关联，将子频带信号其中之一的延迟应用到分析滤波器组上游的宽频带输入音频信号并将剩余的延迟应用到分析滤波器组下游的剩余子频带信号。

5. 发明授权

US08949303B2 Filter 有权
标题翻译：过滤
公开(公告)号：US08949303B2
公开(公告)日：2015-02-03
申请号：US12997233
申请日：2009-06-01
申请人： Kazuo Toraichi , Shuji Kawasaki
发明人： Kazuo Toraichi , Shuji Kawasaki
IPC分类号： G06F17/10 , H03H17/06 , H03H17/02
CPC分类号： H03H17/06 , H03H17/0229
摘要： Provided is an FIR filter capable of obtaining predetermined characteristics with a small number of input taps, delay circuits, and multipliers and achieving an improved response and low cost. In a low-pass filter, a band-pass filter, and a high-pass filter based on an FIR filter, a basic filter is configured that gives a basic impulse response function and has a filter coefficient determined from the impulse response function. Filters having different frequency characteristics are configured by changing the time scale or frequency scale of the basic filter. These filters having different frequency characteristics are combined in a cascade form or a step form, thereby constructing an FIR filter having a small number of taps.
摘要翻译：提供了能够以少量的输入抽头，延迟电路和乘法器获得预定特性并实现改进的响应和低成本的FIR滤波器。在低通滤波器，带通滤波器和基于FIR滤波器的高通滤波器中，基本滤波器被配置为提供基本脉冲响应函数并具有从脉冲响应函数确定的滤波器系数。具有不同频率特性的滤波器通过改变基本滤波器的时间尺度或频率标度来配置。具有不同频率特性的这些滤波器以级联形式或阶梯形式组合，从而构造具有少量抽头的FIR滤波器。

6. 发明授权

US08879747B2 Adaptive filtering system 有权
标题翻译：自适应滤波系统
公开(公告)号：US08879747B2
公开(公告)日：2014-11-04
申请号：US13482678
申请日：2012-05-29
申请人： Markus Christoph
发明人： Markus Christoph
IPC分类号： H03B29/00 , H03H17/02 , H03H21/00
CPC分类号： H03H17/0266 , H03H17/0229 , H03H21/0012 , H03H2021/0041
摘要： An audio system with at least one audio channel may include a digital audio processor in which at least one digital filter is implemented for each channel. The digital filter of each channel may include: an analysis filter bank configured to receive a broad-band input audio signal and divide the input audio signal into a plurality of sub-bands, a sub-band filter for each sub-band, and a synthesis filter bank configured to receive the filtered sub-band signals and combine them for providing a broad-band output audio signal. A delay is associated with each sub-band signal, the delay of one of the sub-band signals being applied to the broad-band input audio signal upstream of the analysis filter bank and the residual delays being applied to the remaining sub-band signals downstream of the analysis filter bank.
摘要翻译：具有至少一个音频通道的音频系统可以包括其中为每个通道实现至少一个数字滤波器的数字音频处理器。每个通道的数字滤波器可以包括：分析滤波器组，被配置为接收宽带输入音频信号并将输入音频信号划分成多个子带，每个子带的子带滤波器和合成滤波器组，被配置为接收经滤波的子带信号并将其组合以提供宽带输出音频信号。延迟与每个子带信号相关联，一个子带信号的延迟被施加到分析滤波器组上游的宽带输入音频信号，并且剩余延迟被施加到剩余的子带信号分析滤波器组的下游。

7. 发明授权

US06678320B1 Efficient finite impulse response filter implementation for CDMA waveform generation 有权
标题翻译：用于CDMA波形生成的高效有限脉冲响应滤波器实现
公开(公告)号：US06678320B1
公开(公告)日：2004-01-13
申请号：US09144533
申请日：1998-08-31
申请人： Levent Aydin
发明人： Levent Aydin
IPC分类号： H03H730
CPC分类号： H03H17/06 , H03H17/0229
摘要： A finite impulse response filter including a first circuit for providing plural delayed signals in response to an input signal. A second circuit is included for multiplying respective ones of the delayed signals by a corresponding coefficient and providing a respective intermediate signal in response thereto. A third circuit selectively changes the sign of respective ones of a first set of the intermediate output signals to provide a set of component in-phase signals. A fourth circuit selectively changes the sign of respective ones of a second set of the intermediate output signals to provide a set of component quadrature signals. The component in-phase signals are combined to provide an in-phase output signal and the component quadrature signals are combined to provide a quadrature output signal. In the illustrative implementation, the coefficients are generated in accordance with an industry standard via a storage device such as a register bank. The third and fourth circuits are controlled by a pseudo-noise sequence generator. The inventive implementation affords a considerable degree of efficiency in design in that in-phase and quadrature filter outputs are generated from a single filter thereby obviating the need for a second filter required by conventional teachings.
摘要翻译：一种有限脉冲响应滤波器，包括响应于输入信号提供多个延迟信号的第一电路。包括用于将相应的延迟信号乘以相应系数的第二电路，并响应于此提供相应的中间信号。第三电路选择性地改变第一组中间输出信号中的相应符号以提供一组分量同相信号。第四电路选择性地改变第二组中间输出信号中的相应符号，以提供一组分量正交信号。组合同相信号被组合以提供同相输出信号，并且组合正交信号被组合以提供正交输出信号。在说明性实现中，经由诸如寄存器组的存储装置根据工业标准生成系数。第三和第四电路由伪噪声序列发生器控制。本发明的实施方案在设计方面提供相当程度的效率，因为从单个滤波器产生同相和正交滤波器输出，从而避免了对常规教导所需的第二滤波器的需要。

8. 发明申请

US20150003575A1 Suppression of Fixed-Pattern Jitter Using FIR Filters 有权
标题翻译：使用FIR滤波器抑制固定码型抖动
公开(公告)号：US20150003575A1
公开(公告)日：2015-01-01
申请号：US14321390
申请日：2014-07-01
申请人： ESS Technology, Inc.
发明人： A. Martin Mallinson
IPC分类号： H04L7/00
CPC分类号： H03H17/06 , H03H17/0229 , H03H17/0248 , H03H17/0286 , H03H17/0294 , H03H21/0012 , H03H21/002
摘要： FIR filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component, with the coefficients of the FIR filter selected so that the filter is the equivalent of two combined FIR filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the on signal. In another embodiment, a FIR filter includes a delay line with a total delay longer than the period of the jitter. A signal is passed down the delay line, the number of signal edges that have occurred as the signal passes each delay element in the counted. Drivers corresponding to the delay elements in which a number of signal edges occur at the desired frequency during the period of fixed pattern jitter activate impedance elements attached to those delay elements. A processor configures the activated impedance elements to provide the desired filter response.
摘要翻译：公开了用于补偿固定模式抖动的FIR滤波器及其构造方法。在一个实施例中，FIR滤波器对具有期望频率分量的信号进行滤波，其中选择FIR滤波器的系数，使得滤波器等效于两个组合的FIR滤波器，一个具有滤波器峰值输出频率处的期望频率，其中信号被延迟等于期望从接通信号去除的不同频率的周期的一半的时间的第二。在另一个实施例中，FIR滤波器包括具有比抖动周期长的总延迟的延迟线。信号沿着延迟线传递，当信号通过计数的每个延迟元件时，发生的信号边沿的数量。对应于在固定模式抖动的周期期间以期望频率出现的信号边缘数量的延迟元件的驱动器激活连接到这些延迟元件的阻抗元件。处理器配置激活的阻抗元件以提供期望的滤波器响应。

9. 发明授权

US07529788B2 Digital filter design method and device, digital filter design program, and digital filter 失效
标题翻译：数字滤波器设计方法和设备，数字滤波器设计程序和数字滤波器
公开(公告)号：US07529788B2
公开(公告)日：2009-05-05
申请号：US10907943
申请日：2005-04-21
申请人： Yukio Koyanagi
发明人： Yukio Koyanagi
IPC分类号： G06F17/10
CPC分类号： H03H17/06 , H03H17/0229 , H03H2017/0072
摘要： A digital filter is designed by combining unit filters (L10′, H10′) having a predetermined asymmetric numerical sequence as filter coefficients (H1 to H3). Thus, it is possible to automatically obtain a desired digital filter coefficient only by combining the unit filter. Moreover, a symmetric numerical sequence {−1, 0, 9, 16, 9, 0, −1}/32 is divided at the center into two parts and one of them is used as the asymmetric filter coefficients (H1 to H3). This reduces the number of taps required for the digital filter designed, eliminates use of a window function, and prevents generation of a discretization error in the filter characteristic obtained.
摘要翻译：通过将具有预定的非对称数字序列的单元滤波器（L10'，H10'）组合为滤波器系数（H1至H3）来设计数字滤波器。因此，可以通过组合单位滤波器来自动获得期望的数字滤波器系数。此外，将对称数字序列{-1,0,9,16,9,0，-1} / 32在中心分成两部分，其中一个被用作非对称滤波器系数（H1至H3）。这减少了设计的数字滤波器所需的抽头数量，消除了使用窗口功能，并且防止了所获得的滤波器特性中的离散化误差的产生。

10. 发明申请

US20070276892A1 FINITE IMPULSE RESPONSE FILTER AND DIGITAL SIGNAL RECEIVING APPARATUS 有权
标题翻译：有限冲突响应滤波器和数字信号接收装置
公开(公告)号：US20070276892A1
公开(公告)日：2007-11-29
申请号：US11833030
申请日：2007-08-02
申请人： Hidekuni YOMO , Yoshinori KUNIEDA , Yuuri YAMAMOTO
发明人： Hidekuni YOMO , Yoshinori KUNIEDA , Yuuri YAMAMOTO
IPC分类号： G06F17/10
CPC分类号： H03H17/0657 , H03H17/0223 , H03H17/0229 , H03H17/06 , H03H17/0621 , H03H2218/085
摘要： An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.
摘要翻译： A / D转换部分以符号速率M倍的模拟信号执行过采样，以将模拟信号转换为数字信号。 FIR滤波部分具有两个具有多个延迟元件的延迟元件序列。两个延迟元件序列具有不同的延迟方向，即正向和反向。可以切换延迟方向，并且根据具有这种延迟元件序列的有限脉冲响应列，进行卷积计算。相位确定部确定在判定部中作出判定所使用的相位。决定部分使用在相位确定部分中确定的相位来对滤波信号做出决定以产生位数据。因此，实现了数字信号接收装置，其在不增加过采样数量的情况下确定高精度的相位，并且在具有减小的电路规模的情况下执行快速计算。

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