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1. 发明授权

US6092227A Test circuit 失效
标题翻译：测试电路
公开(公告)号：US6092227A
公开(公告)日：2000-07-18
申请号：US18934
申请日：1998-02-05
申请人： Hideki Toki , Akira Kitaguchi , Makoto Hatakenaka , Kiyoyuki Shiroshima , Masaaki Matsuo , Tsuyoshi Saitoh
发明人： Hideki Toki , Akira Kitaguchi , Makoto Hatakenaka , Kiyoyuki Shiroshima , Masaaki Matsuo , Tsuyoshi Saitoh
IPC分类号： G01R31/28 , G06F11/22 , G11C11/413 , G11C29/10 , G11C29/34 , G11C29/36 , G11C29/38 , G11C29/56
CPC分类号： G11C29/34 , G11C29/36 , G11C29/38 , G11C29/10
摘要： A test circuit includes a writing unit that outputs m-bit data captured upon receipt of a clock signal, branches the m-bit data n identical m-bit data signals, and stores the n m-bit data signals in a memory device. A function determining unit reads the n m-bit data signals from the memory, compares one of the n m-bit data signals to an m-bit expected value, and determines coincidence or non-coincidence between the n m-bit data signal and an expected value.
摘要翻译：测试电路包括写入单元，其输出接收到时钟信号时捕获的m位数据，分配m位数据n个相同的m位数据信号，并将n个m位数据信号存储在存储器件中。功能确定单元从存储器读取n个m位数据信号，将n个m位数据信号中的一个与m位预期值进行比较，并且确定n个m位数据信号和一个预期的价值。

2. 发明授权

US6114866A Semiconductor device test board and method for evaluating semiconductor devices 失效
标题翻译：半导体器件测试板和半导体器件评估方法
公开(公告)号：US6114866A
公开(公告)日：2000-09-05
申请号：US18445
申请日：1998-02-04
申请人： Masaaki Matsuo , Tsuyoshi Saitoh , Takekazu Yamashita , Michio Nakajima , Akira Kitaguchi , Hideki Toki
发明人： Masaaki Matsuo , Tsuyoshi Saitoh , Takekazu Yamashita , Michio Nakajima , Akira Kitaguchi , Hideki Toki
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , G01R35/00 , G01R31/02
CPC分类号： G01R31/2863 , H01L2924/0002
摘要： A semiconductor device test board solves a problem with conventional test boards in that test results obtained through a burn-in procedure could be identified only before the test board is taken out of a burn-in oven. Hence, conventional test boards required additional steps for checking the test results after removing the test boards from the burn-in oven. This extra step prevents the efficiency of the test from being improved. One embodiment of the present test board has indicator arms, each rotatably mounted on a pivot on the test board, for indicating, in response to a signal on a signal line, the test result of the semiconductor device associated with it. Each of the indicator arms maintains its rest position when no failure has occurred in the semiconductor device associated with it during the test. Each indicator arm changes its position if a failure has occurred in the semiconductor device during the test, and retains one of the two positions until after the test board is taken out of the burn-in oven. Thus, the test result can be determined after taking out the test board from the burn-in oven.
摘要翻译：半导体器件测试板解决了常规测试板的问题，因为只有在将测试板从老化炉中取出之前，才能识别通过烧录程序获得的测试结果。因此，常规测试板需要额外的步骤，以便在从老化炉中取出测试板后检查测试结果。这个额外的步骤可以防止测试的效率得到改善。本测试板的一个实施例具有指示臂，每个指示臂可旋转地安装在测试板上的枢轴上，用于响应于信号线上的信号，指示与其相关联的半导体器件的测试结果。当在测试期间与其相关联的半导体器件中没有发生故障时，每个指示器臂保持其静止位置。如果在测试期间在半导体器件中发生故障，则每个指示臂改变其位置，并且保持两个位置中的一个，直到将测试板从老化炉中取出。因此，可以在从老化炉中取出测试板之后确定测试结果。

3. 发明授权

US5973953A Semiconductor memory device having improved bit line structure 失效
标题翻译：具有改进的位线结构的半导体存储器件
公开(公告)号：US5973953A
公开(公告)日：1999-10-26
申请号：US38278
申请日：1998-03-11
申请人： Takekazu Yamashita , Kiyoyuki Shiroshima , Michio Nakajima , Makoto Hatakenaka , Hideki Toki , Tuyoshi Saitoh
发明人： Takekazu Yamashita , Kiyoyuki Shiroshima , Michio Nakajima , Makoto Hatakenaka , Hideki Toki , Tuyoshi Saitoh
IPC分类号： H01L21/3205 , G11C5/06 , H01L21/8242 , H01L23/52 , H01L27/108
CPC分类号： G11C5/063
摘要： A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.
摘要翻译：半导体存储器件被构造成使得当第一布线层提供第一公共互补数据线对的位线并且第三布线层提供第二公共互补数据线对的位线时，第二布线层使得第二公共互补数据线对的位线和位线之间的重叠区域等于第一公共互补数据线对的位线，以及第一公共补充数据线对的位线和位线之间的重叠区域互补数据线对等于第二公共互补数据线对的位线。

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