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1. 发明授权

US06423815B1 Layer insulating film for multilayer interconnection, resin used therefor and process for producing the same 失效
标题翻译：用于多层互连的层绝缘膜，用于其的树脂及其制造方法
公开(公告)号：US06423815B1
公开(公告)日：2002-07-23
申请号：US09650703
申请日：2000-08-29
申请人： Michio Nakajima , Maki Tokuhiro , Hidenori Saito , Saiko Yoshihashi
发明人： Michio Nakajima , Maki Tokuhiro , Hidenori Saito , Saiko Yoshihashi
IPC分类号： C08G6344
CPC分类号： C08G73/02 , C08G73/22 , H01L23/49894 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a layer insulating film for multilayer interconnection of semiconductors which is excellent in resistance to heat, resistance to moisture absorption as well as in electric characteristic properties, and a process for producing the film. That is, a layer insulating film for multilayer interconnection of semiconductors which comprises a fluorine-containing polybenzoxazole resin having the structure represented by the formula (6) and obtained by a process which comprises subjecting to heat-dehydrating ring closure a fluorine-containing polyhydroxyamide resin obtained by reacting a dicarboxylic acid diester obtained from one kind of compound selected from the group of compounds represented by the formulas (2) and 2,2′-bis(tri-fluoromethyl)-4,4′-biphenyldicarboxylic acid, with 2,2-bis(3-amino-4-hydroxyphenyl)hexafluoropropane, (in the formula (6), m is an integer of 10-500).
摘要翻译：本发明提供了耐热性，耐吸湿性以及电特性的半导体多层互连用层间绝缘膜及其制造方法。也就是说，用于半导体多层互连的层绝缘膜包括具有由式（6）表示的结构的含氟聚苯并恶唑树脂，该方法包括将含氟聚羟基酰胺树脂进行热脱水闭环通过使从由式（2）表示的一组化合物和2,2'-双（三氟甲基）-4,4'-联苯二羧酸中选择的一种化合物获得的二羧酸二酯与2，（3-氨基-4-羟基苯基）六氟丙烷，（式（6）中，m为10〜500的整数）。

2. 发明授权

US6043522A Field effect transistor array including doped two-cell isolation region for preventing latchup 失效
标题翻译：场效应晶体管阵列包括用于防止闭锁的掺杂的二单元隔离区
公开(公告)号：US6043522A
公开(公告)日：2000-03-28
申请号：US61090
申请日：1998-04-16
申请人： Michio Nakajima , Makoto Hatakenaka , Akira Kitaguchi , Kiyoyuki Shiroshima , Takekazu Yamashita , Masaaki Matsuo
发明人： Michio Nakajima , Makoto Hatakenaka , Akira Kitaguchi , Kiyoyuki Shiroshima , Takekazu Yamashita , Masaaki Matsuo
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/105
CPC分类号： H01L27/105 , H01L21/761 , Y10S257/901 , Y10S257/909
摘要： A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.
摘要翻译：能够解决现有的半导体器件的问题的半导体器件的原因在于，由于包括一对相邻地设置的一对N阱和P阱的每个单元需要单独地闭锁的对策，所以不能期望高密度积分。高密度集成防止锁定的有效对策。本半导体装置将N个阱和P个阱的排列方向相邻的两个电池相反地配置，使得两个相邻电池的两个P阱（或两个N阱）相继配置，并且包括隔离层延伸穿过两个相邻的电池以封闭两个连续设置的P阱，从而将两个P阱与衬底共同隔离。

3. 发明授权

US6040614A Semiconductor integrated circuit including a capacitor and a fuse element 失效
标题翻译：包括电容器和熔丝元件的半导体集成电路
公开(公告)号：US6040614A
公开(公告)日：2000-03-21
申请号：US33611
申请日：1998-03-03
申请人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
发明人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/105 , H01L27/108 , H01L29/40
CPC分类号： H01L23/5258 , H01L27/105 , H01L27/108 , H01L2924/0002
摘要： A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.
摘要翻译：半导体集成电路包括位于绝缘层上的熔丝元件。绝缘层的表面基本上是光滑的。绝缘层位于电容器的上方。接线位于绝缘层上。熔丝元件和布线包括相同的材料。

4. 发明授权

US5696643A Disk drive apparatus and read error recovery method in a disk drive apparatus 失效
标题翻译：磁盘驱动装置中的磁盘驱动装置和读取错误恢复方法
公开(公告)号：US5696643A
公开(公告)日：1997-12-09
申请号：US632787
申请日：1996-04-17
申请人： Kazushi Tsuwako , Fujio Harako , Katsumi Suda , Michio Nakajima , Isao Yoneda , Kenji Ogasawara
发明人： Kazushi Tsuwako , Fujio Harako , Katsumi Suda , Michio Nakajima , Isao Yoneda , Kenji Ogasawara
IPC分类号： G11B5/60 , G11B19/04 , G11B19/20 , G11B23/50 , G11B15/46
CPC分类号： G11B5/6005 , G11B19/04 , G11B19/20 , G11B23/505
摘要： A disk drive apparatus and read error recovery method in a disk drive apparatus removes thermal asperities on disk surfaces. A projection, such as a thermal asperity, on the recording surfaces of disks is detected when a signal transducer contacts the projection. The flying height of the signal transducer is lowered, e.g., by reducing the disk rotation speed from the normal rotation speed in read/write operations, while the signal transducer is positioned over the detected projection on the track. The signal transducer strikes the projection to break the projection. This avoids a subsequent error from being caused by the thermal asperity.
摘要翻译：磁盘驱动装置中的磁盘驱动装置和读取错误恢复方法去除磁盘表面上的热凹凸。当信号传感器接触投影时，检测在盘的记录表面上的诸如热不均匀性的投影。信号传感器的飞行高度例如通过在读/写操作中将盘旋转速度从正常旋转速度减小而信号换能器位于轨道上检测到的投影上方。信号传感器撞击投影以断开投影。这避免了由热不均匀引起的后续错误。

5. 发明授权

US5349555A Redundancy circuit 失效
标题翻译：冗余电路
公开(公告)号：US5349555A
公开(公告)日：1994-09-20
申请号：US52629
申请日：1993-04-27
申请人： Michio Nakajima
发明人： Michio Nakajima
IPC分类号： G11C29/00 , G11C29/04 , G11C11/40
CPC分类号： G11C29/781 , G11C29/785
摘要： In order to obtain a redundancy circuit which can freely arrange its fuse in a required position with disciplined accessibility after employment, a combination circuit (50) receives outputs (QA0 to QA7) obtained by decoding a column address (AXM) by a column line decoder (2), signals (QB0 to QB7) indicating a faulty line, signals (L0 to L7) generated from the signals (QB0 to QB7) and an inverted signal (ENB*), to generate signals (YS0 to YS8) for controlling selecting switches for specifying column lines. If a K-th column line is faulty, a column line selecting switch for selecting the K-th column line is forcibly turned off and an (N+1)-th column line is allocated with respect to specification of an N-th column line (N.gtoreq.K). Thus, fuse positions of redundancy circuits can be standarlized between products so that the products can be easily mass-produced and supplied at a low cost even if the redundancy circuits are contained in small quantities of various ASICs.
摘要翻译：为了获得能够在使用后能够自由地将其熔丝自由地布置在所需位置上的冗余电路，组合电路（50）接收通过列线解码器对列地址（AXM）进行解码而获得的输出（QA0至QA7）（QB0〜QB7）生成的信号（QB0〜QB7）和反相信号（ENB *）产生的信号（QB0〜QB7），产生用于控制选择的信号（YS0〜YS8）用于指定列线的开关。如果第K列列故障，则用于选择第K列列的列线选择开关被强制关闭，并且关于第N列的指定分配第（N + 1）列行线（N> / = K）。因此，冗余电路的熔丝位置可以在产品之间标准化，使得即使冗余电路包含在少量各种ASIC中，产品也可以以低成本容易地批量生产和供应。

6. 发明授权

US5293346A Simplified serial selection circuit for serial access in semiconductor memory and operating method thereof 失效
标题翻译：用于半导体存储器中串行存取的简化串行选择电路及其操作方法
公开(公告)号：US5293346A
公开(公告)日：1994-03-08
申请号：US760470
申请日：1991-09-17
申请人： Michio Nakajima , Yukio Miyazaki
发明人： Michio Nakajima , Yukio Miyazaki
IPC分类号： G11C7/00 , G11C8/04
CPC分类号： G11C8/04
摘要： A serial selection circuit is disclosed for sequentially selecting a word line in a semiconductor memory. Flipflops (latch circuits) for respectively holding the state are connected to each word line W0 to W1023. These flipflops are sequentially activated in response to two-phase non-overlap clock signals, and then deactivated. This serial selection circuit has the circuit structure being highly simplified compared with the conventional row decoder, so that the occupied area on the semiconductor chip is substantially reduced.
摘要翻译：公开了用于在半导体存储器中顺序选择字线的串行选择电路。用于分别保持该状态的触发器（锁存电路）连接到每个字线W0至W1023。这些触发器响应于两相非重叠时钟信号被依次激活，然后被去激活。与常规行解码器相比，该串行选择电路具有高度简化的电路结构，使得半导体芯片上的占用面积显着减小。

7. 发明授权

US6127694A Semiconductor wafer and method of manufacturing the same, and semiconductor device and test board of the same 失效
标题翻译：半导体晶片及其制造方法，以及半导体器件及其测试板
公开(公告)号：US6127694A
公开(公告)日：2000-10-03
申请号：US77926
申请日：1993-06-18
申请人： Michio Nakajima
发明人： Michio Nakajima
IPC分类号： G01R31/26 , G01R31/28 , H01L21/326 , H01L21/66 , H01L21/822 , H01L27/04 , H01L23/58 , H01L29/00
CPC分类号： G01R31/2856 , G01R31/2884
摘要： Regarding a semiconductor device, a burn-in board can be standardized in each package. An IC (100) includes a VCC terminal (2), a GND terminal (3), input terminals (4a, 4b), and output terminals (5), and it also includes a burn-in board setting terminal (14). Input signals applied to the input terminals (4a, 4b) are transmitted to gates 16a and 16b of switching circuit (15) and processed in a function block (7). Regardless of the signals applied to the input terminals (4a, 4b), simply applying a test signal to the burn-in board setting terminal (14), a specified logic is applied to the function block (7). Only if a pin arrangement of the VCC terminal (2), the GND terminal (3), and the burn-in board setting terminal (14) is standardized and determined, burn-in can be performed indifferent of another pin arrangement of the input terminals (4a, 4b).
摘要翻译：关于半导体器件，可以在每个封装中标准化老化板。 IC（100）包括VCC端子（2），GND端子（3），输入端子（4a，4b）和输出端子（5），并且还包括老化板设置端子（14）。施加到输入端子（4a，4b）的输入信号被传送到开关电路（15）的门16a和16b，并在功能块（7）中进行处理。无论施加到输入端子（4a，4b）的信号如何，只需将测试信号施加到老化板设置端子（14），就将功能块（7）施加指定的逻辑。只有当VCC端子（2），GND端子（3）和老化板设置端子（14）的引脚布置被标准化和确定时，可以对输入的另一引脚布置无任何老化端子（4a，4b）。

8. 发明授权

US5973953A Semiconductor memory device having improved bit line structure 失效
标题翻译：具有改进的位线结构的半导体存储器件
公开(公告)号：US5973953A
公开(公告)日：1999-10-26
申请号：US38278
申请日：1998-03-11
申请人： Takekazu Yamashita , Kiyoyuki Shiroshima , Michio Nakajima , Makoto Hatakenaka , Hideki Toki , Tuyoshi Saitoh
发明人： Takekazu Yamashita , Kiyoyuki Shiroshima , Michio Nakajima , Makoto Hatakenaka , Hideki Toki , Tuyoshi Saitoh
IPC分类号： H01L21/3205 , G11C5/06 , H01L21/8242 , H01L23/52 , H01L27/108
CPC分类号： G11C5/063
摘要： A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.
摘要翻译：半导体存储器件被构造成使得当第一布线层提供第一公共互补数据线对的位线并且第三布线层提供第二公共互补数据线对的位线时，第二布线层使得第二公共互补数据线对的位线和位线之间的重叠区域等于第一公共互补数据线对的位线，以及第一公共补充数据线对的位线和位线之间的重叠区域互补数据线对等于第二公共互补数据线对的位线。

9. 发明授权

US5926429A Semiconductor memory device and method of refreshing semiconductor memory device 失效
标题翻译：半导体存储器件和刷新半导体存储器件的方法
公开(公告)号：US5926429A
公开(公告)日：1999-07-20
申请号：US199050
申请日：1998-11-24
申请人： Tsuyoshi Saitoh , Kiyoyuki Shiroshima , Michio Nakajima , Masaaki Matsuo , Nobuyuki Fujii , Akira Kitaguchi
发明人： Tsuyoshi Saitoh , Kiyoyuki Shiroshima , Michio Nakajima , Masaaki Matsuo , Nobuyuki Fujii , Akira Kitaguchi
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device includes memory elements, each maintaining memory contents within a period of time during which a refresh operation is repeated, and a refresh request circuit for making a refresh request. The semiconductor memory device includes refreshing circuits each of which, in response to a refresh request from the refresh request circuit, performs a refresh operation on a different number of memory elements at the same time, and a selecting circuit for selecting one refreshing circuit from among the refreshing circuits according to the number of memory elements included in the semiconductor memory device. The refresh request circuit can change the interval at which it makes a refresh request.
摘要翻译：半导体存储器件包括存储器元件，每个存储器元件在重复刷新操作的时间段内保持存储器内容，以及刷新请求电路。半导体存储器件包括刷新电路，每个刷新电路响应于来自刷新请求电路的刷新请求同时对不同数量的存储器元件执行刷新操作，以及选择电路，用于从其中选择一个刷新电路根据包括在半导体存储器件中的存储元件的数量的刷新电路。刷新请求电路可以改变刷新请求的间隔。

10. 发明授权

US5353253A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5353253A
公开(公告)日：1994-10-04
申请号：US126636
申请日：1993-09-27
申请人： Michio Nakajima
发明人： Michio Nakajima
IPC分类号： G11C29/00 , G11C29/04 , G11C7/00 , G11C11/40
CPC分类号： G11C29/76
摘要： A smaller, high-speed, semiconductor memory device having redundancy is disclosed which attains an improved mass productivity. Where a main memory (20) includes a defective memory cell, a defective address designating circuit (21) stores the address of the defective memory cell. Defective address detecting circuits (22a to 22r) detect whether an address signal received at an address signal input terminal (4) coincides with an address signal from the defective address designating circuit (21). If a signal indicative of the coincidence is given to a redundancy memory circuit (23) from the defective address detecting circuits (22a to 22r), data is written in or read from defective address remedy latch circuit groups (23a to 23r) of the redundancy memory circuit (23) which correspond to the defective address detecting circuits (22a to 22r). A data selector (24) selectively outputs data received from the defective address remedy latch circuit groups (23a to 23r) or data received from the main memory (20). Thus, the redundancy memory circuit (23), which requires less space, quickly replaces the defective memory cell of the main memory (20).
摘要翻译：公开了具有冗余的较小的高速半导体存储器件，其具有提高的批量生产率。在主存储器（20）包括缺陷存储单元的情况下，缺陷地址指定电路（21）存储有缺陷存储单元的地址。检测地址检测电路（22a〜22r）是否检测到在地址信号输入端子（4）接收到的地址信号是否与来自缺陷地址指定电路（21）的地址信号一致。如果从缺陷地址检测电路（22a〜22r）向冗余存储电路（23）发出了表示一致的信号，则将数据写入冗余存储电路（23）至缺陷地址补救锁存电路组（23a〜23r）存储电路（23），其对应于缺陷地址检测电路（22a〜22r）。数据选择器（24）选择性地输出从缺陷地址补救锁存电路组（23a至23r）接收的数据或从主存储器（20）接收的数据。因此，需要较少空间的冗余存储器电路（23）快速地替换主存储器（20）的有缺陷的存储单元。

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