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1. 发明授权

US07750365B2 Insulated gate bipolar transistor with built-in freewheeling diode 有权
标题翻译：具有内置续流二极管的绝缘栅双极晶体管
公开(公告)号：US07750365B2
公开(公告)日：2010-07-06
申请号：US12099599
申请日：2008-04-08
申请人： Hideki Takahashi , Shinji Aono
发明人： Hideki Takahashi , Shinji Aono
IPC分类号： H01L29/739
CPC分类号： H01L29/66333 , H01L29/0696 , H01L29/0834 , H01L29/7395
摘要： An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer of a second conductivity type on the second main surface and vertically aligned with a region of the first main electrode in contact with the base region, and a second main electrode formed on the first and second semiconductor layers. An interface between the second main electrode and each of the first and second semiconductor layers is parallel to the first main surface, a distance between the first main surface and the interface is equal to 200 μm or smaller, and a thickness of each of the first and second semiconductor layers is equal to 2 μm or smaller.
摘要翻译：绝缘栅双极晶体管包括在第一主表面上并与第一主表面上的绝缘栅晶体管的基极区接触的第一主电极，在第二主表面上具有第一导电类型的第一半导体层，第二主表面上的第二导电类型的第二半导体层，在第二主表面上具有第二导电类型的半导体层，并且与第一主电极的与基极区域接触的区域垂直对准，以及形成在第一和第二半导体层上的第二主电极。第二主电极与第一和第二半导体层中的每一个之间的界面平行于第一主表面，第一主表面和界面之间的距离等于200μm或更小，并且第一主表面并且第二半导体层等于2μm或更小。

2. 发明授权

US06909142B2 Semiconductor device including a channel stop structure and method of manufacturing the same 有权
公开(公告)号：US06909142B2
公开(公告)日：2005-06-21
申请号：US10133422
申请日：2002-04-29
申请人： Hideki Takahashi , Shinji Aono
发明人： Hideki Takahashi , Shinji Aono
IPC分类号： H01L21/336 , H01L21/762 , H01L21/765 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L21/765 , H01L29/0638 , H01L29/402 , H01L29/407 , H01L29/66734 , H01L29/7811
摘要： It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N−-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N−-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N−-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N−-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N−-type silicon substrate (1). The aluminum electrode (8) is extended over the silicon oxide film (2) to constitute a field plate.

3. 发明申请

US20050017290A1 Insulated gate bipolar transistor with built-in freewheeling diode 审中-公开
标题翻译：具有内置续流二极管的绝缘栅双极晶体管
公开(公告)号：US20050017290A1
公开(公告)日：2005-01-27
申请号：US10826391
申请日：2004-04-19
申请人： Hideki Takahashi , Shinji Aono
发明人： Hideki Takahashi , Shinji Aono
IPC分类号： H01L21/331 , H01L21/336 , H01L27/04 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/76 , H01L29/78
CPC分类号： H01L29/66333 , H01L29/0696 , H01L29/0834 , H01L29/7395
摘要： In an IGBT with a built-in freewheeling diode, a thickness (D) of a polished wafer is equal to 200 μm or smaller, and each of respective thicknesses (T8) and (T9) of an N+-type cathode layer (8) and a P+-type collector layer (9) is equal to 2 μm or smaller. Further, a total width of the N+-type cathode layer (8) and the P+-type collector layer (9) which extends along a width direction (X) is in a range from 50 μm to 200 μm. In this case, an interface (IF2) between a collector electrode (10) and the P+-type collector layer (9) occupies 30-80% of an interface (IF) between the collector electrode (10) and the P+-type collector layer (9) plus the N+-type cathode layer (8).
摘要翻译：在具有内置续流二极管的IGBT中，抛光晶片的厚度（D）等于200μm或更小，N +型阴极层的各自厚度（T8）和（T9）（8）和P +型集电极层（9）等于2μm以下。此外，沿着宽度方向（X）延伸的N +型阴极层（8）和P +型集电体层（9）的总宽度在50μm〜200μm的范围内。在这种情况下，集电极（10）与P +型集电极层（9）之间的界面（IF2）占集电极（10）和P（P）之间的界面（IF）的30〜80％ +型集电极层（9）加上N +型阴极层（8）。

4. 发明授权

US06838744B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06838744B2
公开(公告)日：2005-01-04
申请号：US10273116
申请日：2002-10-18
申请人： Hideki Takahashi , Shinji Aono
发明人： Hideki Takahashi , Shinji Aono
IPC分类号： H01L21/60 , H01L23/485 , H01L27/08 , H01L29/47 , H01L29/872 , H01L27/095 , H01L21/00
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L27/0814 , H01L29/0619 , H01L29/872 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05169 , H01L2224/05556 , H01L2224/05624 , H01L2224/45015 , H01L2224/45124 , H01L2224/48463 , H01L2224/48724 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/2076 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device and a manufacturing method therefor are provided, the semiconductor device having a good reverse recovery characteristic, and having no reduction in breakdown voltage because no defect occurs in the upper main surface of a Si substrate even when wires are bonded onto an anode electrode. A semiconductor device includes a Si substrate including an N+ cathode layer and an N− layer. An impurity such as platinum whose barrier height is less than that of silicon is introduced into upper regions of the N− layer where P anode layers are not formed, thereby forming Schottky junction regions. A barrier metal is formed between the Si substrate and an anode electrode.

5. 发明授权

US07986003B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07986003B2
公开(公告)日：2011-07-26
申请号：US11828616
申请日：2007-07-26
申请人： Shinji Aono , Hideki Takahashi , Yoshifumi Tomomatsu , Junichi Moritani
发明人： Shinji Aono , Hideki Takahashi , Yoshifumi Tomomatsu , Junichi Moritani
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0834 , H01L29/1095 , H01L29/66348
摘要： A carrier storage layer is located in a region of a predetermined depth from a surface of an N− substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N− substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N− substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.
摘要翻译：载体存储层位于距离N基板的表面的预定深度的区域中，基极区域位于比预定深度更浅的区域中，并且发射极区域位于N基板的表面中。载体存储层由注入的磷形成，以在预定深度具有最大杂质浓度，基底区域由注入的硼形成，使其具有比预定深度更浅的位置的最大杂质浓度，并且发射极区域由砷形成注入到在N-底物的表面具有最大的杂质浓度。形成开口以延伸穿过发射极区域，基极区域和载流子存储层。在开口的内壁上形成有栅极绝缘膜。

6. 发明授权

US07189620B2 Semiconductor device including a channel stop structure and method of manufacturing the same 有权
标题翻译：包括通道停止结构的半导体器件及其制造方法
公开(公告)号：US07189620B2
公开(公告)日：2007-03-13
申请号：US11123192
申请日：2005-05-06
申请人： Hideki Takahashi , Shinji Aono
发明人： Hideki Takahashi , Shinji Aono
IPC分类号： H01L21/4763 , H01L31/119 , H01L29/94
CPC分类号： H01L29/7813 , H01L21/765 , H01L29/0638 , H01L29/402 , H01L29/407 , H01L29/66734 , H01L29/7811
摘要： It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N−-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N−-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N−-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N−-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N−-type silicon substrate (1). The aluminum electrode (8) is extended over the silicon oxide film (2) to constitute a field plate.
摘要翻译：本发明的目的是获得一种包括稳定击穿电压的效果优异的通道阻挡结构的半导体器件和制造该半导体器件的方法。在N + O型硅衬底（1）的上表面上形成氧化硅膜（2）。在N，P型硅衬底（1）的上表面（3）中形成一个N + + +型杂质注入区（4）氧化硅膜（2）。在N + +型硅衬底的上表面（3）中形成比N + +型杂质注入区（4）更深的沟槽（5） 1）。在沟槽（5）的内壁上形成氧化硅膜（6）。形成多晶硅膜（7）以填充沟槽（5）。在N + - 型硅衬底（1）的上表面（3）上形成铝电极（8）。铝电极（8）设置成与多晶硅膜（7）的上表面和氮化硅衬底（1）的上表面（3）接触。铝电极（8）在氧化硅膜（2）上延伸以构成场板。

7. 发明申请

US20050233542A1 Semiconductor device including a channel stop structure and method of manufacturing the same 审中-公开
公开(公告)号：US20050233542A1
公开(公告)日：2005-10-20
申请号：US11143734
申请日：2005-06-03
申请人： Hideki Takahashi , Shinji Aono
发明人： Hideki Takahashi , Shinji Aono
IPC分类号： H01L21/336 , H01L21/762 , H01L21/765 , H01L29/06 , H01L29/40 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/765 , H01L29/0638 , H01L29/402 , H01L29/407 , H01L29/66734 , H01L29/7811
摘要： It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N−-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N−-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N−-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N−-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N−-type silicon substrate (1). The aluminum electrode (8) is extended over the silicon oxide film (2) to constitute a field plate.

8. 发明申请

US20050208723A1 Semiconductor device including a channel stop structure and method of manufacturing the same 有权
标题翻译：包括通道停止结构的半导体器件及其制造方法
公开(公告)号：US20050208723A1
公开(公告)日：2005-09-22
申请号：US11123192
申请日：2005-05-06
申请人： Hideki Takahashi , Shinji Aono
发明人： Hideki Takahashi , Shinji Aono
IPC分类号： H01L21/336 , H01L21/762 , H01L21/765 , H01L29/06 , H01L29/40 , H01L29/78 , H01L21/4763 , H01L31/119 , H01L29/94
CPC分类号： H01L29/7813 , H01L21/765 , H01L29/0638 , H01L29/402 , H01L29/407 , H01L29/66734 , H01L29/7811
摘要： It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N−-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N−-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N−-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N−-type silicon substrate (1). The aluminum electrode (8) is provided in contact with an upper surface of the polysilicon film (7) and the upper surface (3) of the N−-type silicon substrate (1). The aluminum electrode (8) is extended over the silicon oxide film (2) to constitute a field plate.
摘要翻译：本发明的目的是获得一种包括稳定击穿电压的效果优异的通道阻挡结构的半导体器件和制造该半导体器件的方法。在N + O型硅衬底（1）的上表面上形成氧化硅膜（2）。在N，P型硅衬底（1）的上表面（3）中形成一个N + + +型杂质注入区（4）氧化硅膜（2）。在N + +型硅衬底的上表面（3）中形成比N + +型杂质注入区（4）更深的沟槽（5） 1）。在沟槽（5）的内壁上形成氧化硅膜（6）。形成多晶硅膜（7）以填充沟槽（5）。在N + - 型硅衬底（1）的上表面（3）上形成铝电极（8）。铝电极（8）设置成与多晶硅膜（7）的上表面和氮化硅衬底（1）的上表面（3）接触。铝电极（8）在氧化硅膜（2）上延伸以构成场板。

9. 发明申请

US20080197379A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080197379A1
公开(公告)日：2008-08-21
申请号：US11828616
申请日：2007-07-26
申请人： Shinji AONO , Hideki Takahashi , Yoshifumi Tomomatsu , Junichi Moritani
发明人： Shinji AONO , Hideki Takahashi , Yoshifumi Tomomatsu , Junichi Moritani
IPC分类号： H01L29/74 , H01L21/332
CPC分类号： H01L29/7397 , H01L29/0834 , H01L29/1095 , H01L29/66348
摘要： A carrier storage layer is located in a region of a predetermined depth from a surface of an N− substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N− substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N− substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.
摘要翻译：载体存储层位于距离N基板的表面的预定深度的区域中，基极区域位于比预定深度更浅的区域中，并且发射极区域位于N基板的表面中。载体存储层由注入的磷形成，以在预定深度具有最大杂质浓度，基底区域由注入的硼形成，使其具有比预定深度更浅的位置的最大杂质浓度，并且发射极区域由砷形成注入到在N-底物的表面具有最大的杂质浓度。形成开口以延伸穿过发射极区域，基极区域和载流子存储层。在开口的内壁上形成有栅极绝缘膜。

10. 发明申请

US20050258493A1 Reverse conducting semiconductor device and a fabrication method thereof 有权
标题翻译：反向导通半导体器件及其制造方法
公开(公告)号：US20050258493A1
公开(公告)日：2005-11-24
申请号：US11076872
申请日：2005-03-11
申请人： Shinji Aono , Aya Yamamoto , Hideki Takahashi , Kenzo Yamamoto , Ikuko Yamamoto
发明人： Shinji Aono , Aya Yamamoto , Hideki Takahashi , Kenzo Yamamoto , Ikuko Yamamoto
IPC分类号： H01L29/06 , H01L21/322 , H01L21/331 , H01L21/336 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/08 , H01L29/739 , H01L29/76 , H01L29/78
CPC分类号： H01L21/263 , H01L29/0834 , H01L29/7397
摘要： To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type base layer to constitute the insulated gate bipolar transistor; a first conductive type base layer for constituting the insulated gate bipolar transistor, an anode electrode which is an emitter electrode covering a first conductive type emitter layer and the second conductive type base layer, a cathode electrode which is a collector electrode covering the first conductive type base layer and a second conductive type collector layer formed on the part of the first conductive type base layer, wherein a short lifetime region is formed on a part of the first conductive type base layer.
摘要翻译：为了提供一种反向传导半导体器件，其中在衬底上单片地形成具有优异恢复特性的绝缘栅双极晶体管和续流二极管，所述续流二极管包括：第二导电型基极层，用于构成绝缘栅双极晶体管; 用于构成绝缘栅双极晶体管的第一导电型基极层，作为覆盖第一导电型发射极层的发射电极的阳极电极和第二导电型基极层，作为覆盖第一导电型的集电极的阴极电极基底层和形成在第一导电型基底层的一部分上的第二导电类型集电极层，其中在第一导电类型基底层的一部分上形成短寿命区域。

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