会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明授权
    • Phase changeable structure and method of forming the same
    • 相变结构及其形成方法
    • US07569430B2
    • 2009-08-04
    • US11674580
    • 2007-02-13
    • Jun-Soo BaeHideki HoriiJi-Hye YiYoung-Soo Lim
    • Jun-Soo BaeHideki HoriiJi-Hye YiYoung-Soo Lim
    • H01L21/82
    • H01L45/1675H01L45/06H01L45/1233H01L45/144
    • The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.
    • 本发明涉及具有减少的缺陷量的相变结构和形成相变结构的方法。 首先通过(i)在下电极上形成包括硫族化物的相变层来形成堆叠复合体,(ii)形成相对于在相上包括氯的第一蚀刻材料具有第一蚀刻速率的蚀刻停止层 可变层,和(iii)形成相对于蚀刻停止层上的第一蚀刻材料具有第二蚀刻速率的导电层。 然后使用第一蚀刻材料蚀刻层叠复合体的导电层以形成上电极。 然后使用基本上不含氯的第二蚀刻材料来蚀刻蚀刻停止层和相变层,以分别形成蚀刻停止图案和相变图案。
    • 7. 发明授权
    • Probe card and test apparatus including the same
    • 探针卡和测试仪器包括它们
    • US08581612B2
    • 2013-11-12
    • US12817826
    • 2010-06-17
    • Hideki HoriiYoung-kuk KimMi-lim Park
    • Hideki HoriiYoung-kuk KimMi-lim Park
    • G01R31/20
    • G01R31/2889
    • A probe card and a test apparatus including the probe card for improving test reliability. The probe card may include a first input terminal Microelectromechanical Systems (MEMS) switch that connects a first input terminal and a first input probe pin, wherein the first input terminal MEMS switch comprises a control portion that receives an operation signal and a connection portion that connects the first input terminal and the first input probe pin. The probe card may further include a first output terminal MEMS switch that connects a first output terminal and a first output probe pin, wherein the first output terminal MEMS switch comprises a control portion that receives the operation signal and a connection portion that connects the first output terminal and the first output probe pin.
    • 探针卡和测试装置,包括用于提高测试可靠性的探针卡。 探针卡可以包括连接第一输入端和第一输入探针的第一输入端微机电系统(MEMS)开关,其中第一输入端MEMS开关包括接收操作信号的控制部分和连接 第一输入端和第一输入探针。 探针卡还可以包括连接第一输出端和第一输出探针的第一输出端MEMS开关,其中第一输出端MEMS开关包括接收操作信号的控制部分和连接第一输出端 端子和第一个输出探针。
    • 10. 发明申请
    • Phase changeable memory cell array region and method of forming the same
    • 相变存储单元阵列区域及其形成方法
    • US20070111440A1
    • 2007-05-17
    • US11581012
    • 2006-10-16
    • Hyeong-Geun AnHideki HoriiSang-Yeol Kang
    • Hyeong-Geun AnHideki HoriiSang-Yeol Kang
    • H01L21/00H01L21/336H01L29/94
    • H01L45/144H01L27/2436H01L27/2472H01L45/06H01L45/1233H01L45/126H01L45/1293H01L45/165H01L45/1666
    • A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.
    • 相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。 该区域还包括穿过下层间绝缘层设置的多个导电插塞。 所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案,所述相变图案覆盖所述多个导电插塞中的至少两个,其中所述相变材料图案包括多个与第 多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域,其中至少一个第二区域具有比多个第一区域更低的热导率。 相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。 该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。