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    • 2. 发明授权
    • Field effect transistor and method of manufacturing the same
    • 场效应晶体管及其制造方法
    • US08569797B2
    • 2013-10-29
    • US13185818
    • 2011-07-19
    • Hidekazu UmedaMasahiro HikitaTetsuzo Ueda
    • Hidekazu UmedaMasahiro HikitaTetsuzo Ueda
    • H01L29/80
    • H01L29/7783H01L29/1066H01L29/2003H01L29/66462H01L29/7787
    • A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.
    • 场效应晶体管包括形成在衬底上的第一半导体层和第二半导体层。 第一半导体层具有设置为包含非导电杂质的隔离区域的含有区域和不含非导电杂质的非含有区域。 第一区域由容纳区域和非含有区域之间的界面的一部分的附近限定,界面的部分在栅电极下方,包括界面部分的附近包含在包含 地区。 第二半导体层包括位于第一区域正上方的第二区域。 第二区域的非导电性杂质的浓度低于第一区域的浓度。
    • 3. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120119261A1
    • 2012-05-17
    • US13356156
    • 2012-01-23
    • Hidekazu UMEDATetsuzo Ueda
    • Hidekazu UMEDATetsuzo Ueda
    • H01L29/778
    • H01L29/7786H01L29/1029H01L29/1066H01L29/2003H01L29/402H01L29/66462
    • A semiconductor device includes: a substrate 101, a first nitride semiconductor layer 104S which includes a plurality of nitride semiconductor layers formed on the substrate 101, and has a channel region; a second semiconductor layer 105 which is formed on the first nitride semiconductor layer 104S, and has a conductivity type opposite a conductivity type of the channel region; a conductive layer which is in contact with the second semiconductor layer 105, and includes a metal layer 107 or a high carrier concentration semiconductor layer having a carrier concentration of 1×1018 cm−3 or higher; an insulating layer 110 formed on the conductive layer; a gate electrode 111 formed on the insulating layer 110; and a source electrode 108 and a drain electrode 109 formed to laterally sandwich the second semiconductor layer 105.
    • 半导体器件包括:衬底101,包括形成在衬底101上的多个氮化物半导体层的第一氮化物半导体层104S,并具有沟道区; 第二半导体层105,其形成在第一氮化物半导体层104S上,并且具有与沟道区的导电类型相反的导电类型; 与第二半导体层105接触的导体层,具有载流子浓度为1×1018 cm -3以上的金属层107或高载流子浓度半导体层; 形成在导电层上的绝缘层110; 形成在绝缘层110上的栅电极111; 以及形成为横向夹持第二半导体层105的源电极108和漏电极109。
    • 5. 发明授权
    • Semiconductor device including separated gate electrode and conductive layer
    • 半导体器件包括分离的栅电极和导电层
    • US08692292B2
    • 2014-04-08
    • US13356156
    • 2012-01-23
    • Hidekazu UmedaTetsuzo Ueda
    • Hidekazu UmedaTetsuzo Ueda
    • H01L29/66
    • H01L29/7786H01L29/1029H01L29/1066H01L29/2003H01L29/402H01L29/66462
    • A semiconductor device includes: a substrate 101, a first nitride semiconductor layer 104S which includes a plurality of nitride semiconductor layers formed on the substrate 101, and has a channel region; a second semiconductor layer 105 which is formed on the first nitride semiconductor layer 104S, and has a conductivity type opposite a conductivity type of the channel region; a conductive layer which is in contact with the second semiconductor layer 105, and includes a metal layer 107 or a high carrier concentration semiconductor layer having a carrier concentration of 1×1018 cm−3 or higher; an insulating layer 110 formed on the conductive layer; a gate electrode 111 formed on the insulating layer 110; and a source electrode 108 and a drain electrode 109 formed to laterally sandwich the second semiconductor layer 105.
    • 半导体器件包括:衬底101,包括形成在衬底101上的多个氮化物半导体层的第一氮化物半导体层104S,并具有沟道区; 第二半导体层105,其形成在第一氮化物半导体层104S上,并且具有与沟道区的导电类型相反的导电类型; 与第二半导体层105接触的导体层,具有载流子浓度为1×1018 cm -3以上的金属层107或高载流子浓度半导体层; 形成在导电层上的绝缘层110; 形成在绝缘层110上的栅电极111; 以及形成为横向夹持第二半导体层105的源电极108和漏电极109。