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1. 发明授权

US08234428B2 Arbitration device that arbitrates conflicts caused in data transfers 失效
标题翻译：仲裁数据传输引起冲突的仲裁设备
公开(公告)号：US08234428B2
公开(公告)日：2012-07-31
申请号：US13190906
申请日：2011-07-26
申请人： Hidekazu Osano , Takayuki Kinoshita , Yoshikazu Iwami , Makoto Hataida
发明人： Hidekazu Osano , Takayuki Kinoshita , Yoshikazu Iwami , Makoto Hataida
IPC分类号： G06F13/368
CPC分类号： G06F13/36
摘要： An arbitration device including: a first measuring circuit to measure a first period; a second measuring circuit to measure a second period; a second selection circuit to select and output the first period or the second period according to a first selection signal; a first control circuit to output the first selection signal according to the first period and the second period; a third selection circuit to select a third data or either the first data or the second data according to a second selection signal; a third measuring circuit to measure a third period; a fourth measuring circuit to measure a fourth period; and a second control circuit to output the second selection signal according to either the selected first period or the selected second period and the third period and the fourth period.
摘要翻译：一种仲裁装置，包括：第一测量电路，用于测量第一周期; 用于测量第二周期的第二测量电路; 第二选择电路，用于根据第一选择信号选择和输出第一周期或第二周期; 第一控制电路，用于根据第一周期和第二周期输出第一选择信号; 第三选择电路，用于根据第二选择信号选择第三数据或第一数据或第二数据; 测量第三周期的第三测量电路; 测量第四周期的第四测量电路; 以及第二控制电路，用于根据所选择的第一周期或所选择的第二周期以及第三周期和第四周期输出第二选择信号。

2. 发明授权

US08837505B2 Arbitration method, arbiter circuit, and apparatus provided with arbiter circuit 有权
标题翻译：仲裁方法，仲裁器电路和装备有仲裁电路的设备
公开(公告)号：US08837505B2
公开(公告)日：2014-09-16
申请号：US13137846
申请日：2011-09-16
申请人： Makoto Hataida , Toshikazu Ueki , Takayuki Kinoshita , Yoshikazu Iwami , Hidekazu Osano
发明人： Makoto Hataida , Toshikazu Ueki , Takayuki Kinoshita , Yoshikazu Iwami , Hidekazu Osano
IPC分类号： H04L12/54 , H04L12/933 , H04L12/937
CPC分类号： H04L49/101 , H04L49/253
摘要： An arbitration method includes a first process to perform a path control to transfer data from physically plural input ports logically having plural virtual channels to an arbitrary one of the plural output ports, wherein only one channel is selectable at one input port at an arbitrary point in time, by performing an arbitration among the channels of each of the plural input ports according to an arbitrary arbitration algorithm other than a time-division algorithm, and a second process to perform an arbitration among the plural input ports according to the arbitrary arbitration algorithm. The arbitrary arbitration algorithm used in the first and second processes is switched to the time-division algorithm for a predetermined time in response to a trigger.
摘要翻译：一种仲裁方法包括执行路径控制以将逻辑上具有多个虚拟通道的物理多个输入端口的数据传送到多个输出端口中的任意一个的路径控制的第一处理，其中在一个输入端口只有一个通道在任意点可选时间，通过根据除了时分算法之外的任意仲裁算法在多个输入端口中的每一个的信道之间执行仲裁，以及根据任意仲裁算法在多个输入端口之间执行仲裁的第二处理。响应于触发，在第一和第二处理中使用的任意仲裁算法被切换到预定时间的时分算法。

3. 发明授权

US08910007B2 Apparatus and method for error check of transmission data 有权
标题翻译：传输数据错误检查的装置和方法
公开(公告)号：US08910007B2
公开(公告)日：2014-12-09
申请号：US13225066
申请日：2011-09-02
申请人： Takayuki Kinoshita , Hidekazu Osano , Yoshikazu Iwami , Makoto Hataida
发明人： Takayuki Kinoshita , Hidekazu Osano , Yoshikazu Iwami , Makoto Hataida
IPC分类号： H04L1/18 , H04L1/08 , H04L1/16
CPC分类号： H04L1/1854
摘要： An error check apparatus including, a packet protocol error check processing circuit configure to detect a protocol error of a packet, a retry control circuit configured to receive the protocol error of the packet from the packet protocol error check processing circuit, and to perform request for retry for data of the packet if the received protocol error has not been detected from a packet retransmitted by retry request, and an error notification circuit configured to notify of the protocol error of the packet to a processing unit in a higher-level layer if the protocol error is not a first protocol error for the packet.
摘要翻译：一种错误检查装置，包括：分组协议错误检查处理电路，被配置为检测分组的协议错误;重试控制电路，被配置为从分组协议错误检查处理电路接收分组的协议错误，并且执行请求如果从重试请求重发的分组中还没有检测到接收到的协议错误，则重试分组的数据;以及错误通知电路，被配置为如果分组的协议错误通知上级处理单元，则协议错误不是数据包的第一个协议错误。

4. 发明申请

US20110283032A1 ARBITRATION DEVICE 失效
标题翻译：仲裁设备
公开(公告)号：US20110283032A1
公开(公告)日：2011-11-17
申请号：US13190906
申请日：2011-07-26
申请人： Hidekazu OSANO , Takayuki Kinoshita , Yoshikazu Iwami , Makoto Hataida
发明人： Hidekazu OSANO , Takayuki Kinoshita , Yoshikazu Iwami , Makoto Hataida
IPC分类号： G06F13/368
CPC分类号： G06F13/36
摘要： An arbitration device including: a first measuring circuit to measure a first period; a second measuring circuit to measure a second period; a second selection circuit to select and output the first period or the second period according to a first selection signal; a first control circuit to output the first selection signal according to the first period and the second period; a third selection circuit to select a third data or either the first data or the second data according to a second selection signal; a third measuring circuit to measure a third period; a fourth measuring circuit to measure a fourth period; and a second control circuit to output the second selection signal according to either the selected first period or the selected second period and the third period and the fourth period.
摘要翻译：一种仲裁装置，包括：第一测量电路，用于测量第一周期; 用于测量第二周期的第二测量电路; 第二选择电路，用于根据第一选择信号选择和输出第一周期或第二周期; 第一控制电路，用于根据第一周期和第二周期输出第一选择信号; 第三选择电路，用于根据第二选择信号选择第三数据或第一数据或第二数据; 测量第三周期的第三测量电路; 测量第四周期的第四测量电路; 以及第二控制电路，用于根据所选择的第一周期或所选择的第二周期以及第三周期和第四周期输出第二选择信号。

5. 发明申请

US20110320900A1 APPARATUS AND METHOD FOR ERROR CHECK OF TRANSMISSION DATA 有权
标题翻译：传输数据错误检查的装置和方法
公开(公告)号：US20110320900A1
公开(公告)日：2011-12-29
申请号：US13225066
申请日：2011-09-02
申请人： Takayuki Kinoshita , Hidekazu Osano , Yoshikazu Iwami , Makoto Hataida
发明人： Takayuki Kinoshita , Hidekazu Osano , Yoshikazu Iwami , Makoto Hataida
IPC分类号： H04L1/08 , G06F11/14
CPC分类号： H04L1/1854
摘要： An error check apparatus including, a packet protocol error check processing circuit configure to detect a protocol error of a packet, a retry control circuit configured to receive the protocol error of the packet from the packet protocol error check processing circuit, and to perform request for retry for data of the packet if the received protocol error has not been detected from a packet retransmitted by retry request, and an error notification circuit configured to notify of the protocol error of the packet to a processing unit in a higher-level layer if the protocol error is not a first protocol error for the packet.
摘要翻译：一种错误检查装置，包括：分组协议错误检查处理电路，被配置为检测分组的协议错误;重试控制电路，被配置为从分组协议错误检查处理电路接收分组的协议错误，并且执行请求如果从重试请求重发的分组中还没有检测到接收到的协议错误，则重试分组的数据;以及错误通知电路，被配置为如果分组的协议错误通知上级处理单元，则协议错误不是数据包的第一个协议错误。

6. 发明申请

US20110069717A1 Data transfer device, information processing apparatus, and control method 审中-公开
标题翻译：数据传输装置，信息处理装置和控制方法
公开(公告)号：US20110069717A1
公开(公告)日：2011-03-24
申请号：US12926492
申请日：2010-11-22
申请人： Hidekazu Osano , Takayuki Kinoshita , Yoshikazu Iwami , Makoto Hataida
发明人： Hidekazu Osano , Takayuki Kinoshita , Yoshikazu Iwami , Makoto Hataida
IPC分类号： H04L12/56
CPC分类号： G06F13/362 , H04L47/6215
摘要： A data transfer device includes a plurality of input queues, a plurality of arbitration control units provided for the respective input queues, and an input queue selecting unit that selects any one of the input queues based on a priority set for each input queue, and outputs data from the selected input queue. Each arbitration control unit includes a register that stores therein a predetermined upper limit, a counter that counts the amount of data output from a corresponding input queue, and a control circuit that, when a value of the counter becomes equal to or greater than the upper limit stored in the register, causes the input queue selecting unit to update the priority and resets the value of the counter.
摘要翻译：数据传输装置包括多个输入队列，为各个输入队列提供的多个仲裁控制单元，以及输入队列选择单元，其基于为每个输入队列设置的优先级来选择输入队列中的任何一个，并输出来自所选输入队列的数据每个仲裁控制单元包括其中存储有预定上限的寄存器，对从相应输入队列输出的数据量进行计数的计数器，以及当计数器的值等于或大于上限存储在寄存器中的限制，使得输入队列选择单元更新优先级并重置计数器的值。

7. 发明申请

US20120002677A1 Arbitration method, arbiter circuit, and apparatus provided with arbiter circuit 有权
标题翻译：仲裁方法，仲裁器电路和装备有仲裁电路的设备
公开(公告)号：US20120002677A1
公开(公告)日：2012-01-05
申请号：US13137846
申请日：2011-09-16
申请人： Makoto Hataida , Toshikazu Ueki , Takayuki Kinoshita , Yoshikazu Iwami
发明人： Makoto Hataida , Toshikazu Ueki , Takayuki Kinoshita , Yoshikazu Iwami
IPC分类号： H04L12/56
CPC分类号： H04L49/101 , H04L49/253
摘要： An arbitration method includes a first process to perform a path control to transfer data from physically plural input ports logically having plural virtual channels to an arbitrary one of the plural output ports, wherein only one channel is selectable at one input port at an arbitrary point in time, by performing an arbitration among the channels of each of the plural input ports according to an arbitrary arbitration algorithm other than a time-division algorithm, and a second process to perform an arbitration among the plural input ports according to the arbitrary arbitration algorithm. The arbitrary arbitration algorithm used in the first and second processes is switched to the time-division algorithm for a predetermined time in response to a trigger.
摘要翻译：一种仲裁方法包括执行路径控制以将逻辑上具有多个虚拟通道的物理多个输入端口的数据传送到多个输出端口中的任意一个的路径控制的第一处理，其中在一个输入端口只有一个通道在任意点可选时间，通过根据除了时分算法之外的任意仲裁算法在多个输入端口中的每一个的信道之间执行仲裁，以及根据任意仲裁算法在多个输入端口之间执行仲裁的第二处理。响应于触发，在第一和第二处理中使用的任意仲裁算法被切换到预定时间的时分算法。

8. 发明申请

US20110038374A1 Crossbar switch system 失效
标题翻译：交叉开关系统
公开(公告)号：US20110038374A1
公开(公告)日：2011-02-17
申请号：US12926032
申请日：2010-10-21
申请人： Seiji Satta , Akira Okamoto , Takayuki Kinoshita , Makoto Hataida
发明人： Seiji Satta , Akira Okamoto , Takayuki Kinoshita , Makoto Hataida
IPC分类号： H04L12/56
CPC分类号： H04L49/15 , H04L49/101
摘要： Each chip arranged in each crossbar switch creates and issues, if a packet is input, a log collection packet for collecting a log of the packet. Each chip collects a log related to a transfer of the input packet. Each chip embeds, in the issued log collection packet or a log collection packet transferred from a crossbar switch in a previous stage, the collected log. If a transfer destination of the packet is other than the crossbar switches, each chip stores, in a storage space, the log embedded in the log collection packet and then transfers, to the transfer destination, only an original packet in which the log is deleted. In contrast, if the transfer destination is a crossbar switch, each chip transfers the log collection packet to a crossbar switch in a next stage.
摘要翻译：布置在每个交叉开关中的每个芯片在输入数据包时创建并发出用于收集数据包日志的日志收集数据包。每个芯片收集与传输输入数据包相关的日志。每个芯片在发出的日志收集包或从前一个阶段的交叉开关传输的日志收集包中嵌入收集的日志。如果分组的传送目的地不是交叉开关，则每个芯片在存储空间中存储嵌入在日志收集分组中的日志，然后将仅记录日志的原始分组传送到传送目的地。相比之下，如果传输目的地是交叉开关，则每个芯片在下一阶段将日志收集包传送到交叉开关。

9. 发明授权

US08423812B2 Time correction in a semiconductor device using correction information provided by an adjacent semiconductor device 失效
标题翻译：使用由相邻半导体器件提供的校正信息的半导体器件中的时间校正
公开(公告)号：US08423812B2
公开(公告)日：2013-04-16
申请号：US12926596
申请日：2010-11-29
申请人： Akira Okamoto , Seiji Satta , Makoto Hataida , Takayuki Kinoshita
发明人： Akira Okamoto , Seiji Satta , Makoto Hataida , Takayuki Kinoshita
IPC分类号： G06F1/12 , G06F9/00 , G06F9/24 , G06F15/177 , G06F15/16
CPC分类号： G06F1/14
摘要： In an information processing apparatus that includes a first and second semiconductor devices that are connected to each other and also includes a system control device that is connected to the first and second semiconductor devices, the timers that are mounted on the semiconductor devices are all synchronized by successively performing a timer correction process between a semiconductor device in which the timer is synchronized and a semiconductor device, adjacent to the semiconductor device, in which the timer is not synchronized, and, when an error occurs in the information processing device, the value in the synchronized timer and the error information are stored in a predetermined register.
摘要翻译：在包括彼此连接的第一和第二半导体器件的信息处理设备中，还包括连接到第一和第二半导体器件的系统控制器件，安装在半导体器件上的定时器都通过在其中定时器同步的半导体器件与定时器未同步的半导体器件相邻的半导体器件之间连续执行定时器校正处理，并且当在信息处理器件中发生错误时，同步定时器和错误信息被存储在预定的寄存器中。

10. 发明授权

US08780900B2 Crossbar switch system 失效
标题翻译：交叉开关系统
公开(公告)号：US08780900B2
公开(公告)日：2014-07-15
申请号：US12926032
申请日：2010-10-21
申请人： Seiji Satta , Akira Okamoto , Takayuki Kinoshita , Makoto Hataida
发明人： Seiji Satta , Akira Okamoto , Takayuki Kinoshita , Makoto Hataida
IPC分类号： H04L12/28
CPC分类号： H04L49/15 , H04L49/101
摘要： Each chip arranged in each crossbar switch creates and issues, if a packet is input, a log collection packet for collecting a log of the packet. Each chip collects a log related to a transfer of the input packet. Each chip embeds, in the issued log collection packet or a log collection packet transferred from a crossbar switch in a previous stage, the collected log. If a transfer destination of the packet is other than the crossbar switches, each chip stores, in a storage space, the log embedded in the log collection packet and then transfers, to the transfer destination, only an original packet in which the log is deleted. In contrast, if the transfer destination is a crossbar switch, each chip transfers the log collection packet to a crossbar switch in a next stage.
摘要翻译：布置在每个交叉开关中的每个芯片在输入数据包时创建并发出用于收集数据包日志的日志收集数据包。每个芯片收集与传输输入数据包相关的日志。每个芯片在发出的日志收集包或从前一个阶段的交叉开关传输的日志收集包中嵌入收集的日志。如果分组的传送目的地不是交叉开关，则每个芯片在存储空间中存储嵌入在日志收集分组中的日志，然后将仅记录日志的原始分组传送到传送目的地。相比之下，如果传输目的地是交叉开关，则每个芯片在下一阶段将日志收集包传送到交叉开关。

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