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1. 发明授权

US08631152B2 System and method for data packet transmission and reception 失效
标题翻译：数据包发送和接收的系统和方法
公开(公告)号：US08631152B2
公开(公告)日：2014-01-14
申请号：US12385885
申请日：2009-04-22
申请人： Hidekazu Osano , Hiroshi Nakayama
发明人： Hidekazu Osano , Hiroshi Nakayama
IPC分类号： G06F15/16
CPC分类号： G06F13/387
摘要： A system transmits a data packet from a transmitting apparatus to a receiving apparatus. The receiving apparatus includes a receive buffer, and a size specifying information transmitting unit that transmits size specifying information to the transmitting apparatus. The transmitting apparatus includes a transmit buffer, a credit storage unit that stores, as a credit, a value corresponding to a total size of all data packets stored in the receive buffer, a credit adding unit that adds a credit to the stored credit on transmitting a data packet, a credit subtracting unit that specifies a size of a read-out data packet on receiving the size specifying information, subtracts a credit corresponding to the specified size from a stored credit, and a transmission controlling unit that controls data packet transmission based on a credit stored in the credit storage unit.
摘要翻译：系统将数据分组从发送装置发送到接收装置。接收装置包括接收缓冲器和向发送装置发送大小指定信息的大小指定信息发送单元。发送装置包括发送缓冲器，信用存储单元，作为信用存储对应于存储在接收缓冲器中的所有数据分组的总大小的值;信用增加单元，用于向所发送的存储信用增加信用数据分组，信用减除单元，其在接收到大小指定信息时指定读出数据分组的大小，从存储的积分中减去与规定大小相对应的信用，以及控制数据分组发送的发送控制部，存储在信用存储单元中的信用。

2. 发明授权

US07949080B2 Phase adjusting function evaluating method, transmission margin measuring method, information processing apparatus and computer readable information recording medium 有权
标题翻译：相位调整功能评估方法，传输边缘测量方法，信息处理装置和计算机可读信息记录介质
公开(公告)号：US07949080B2
公开(公告)日：2011-05-24
申请号：US11987282
申请日：2007-11-28
申请人： Hiroshi Nakayama , Hidekazu Osano
发明人： Hiroshi Nakayama , Hidekazu Osano
IPC分类号： H03D3/24
CPC分类号： G06F1/10 , H03K5/135 , H03L7/07 , H03L7/0812 , H04L7/0008 , H04L7/0037 , H04L7/0041 , H04L7/02
摘要： A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting operation is stored when the phase amount added to the clock signal or the plurality of data signals is changed.
摘要翻译：在接收装置中添加到时钟信号或用于调整其相位关系的多个数据信号的相位量被改变，并且当相位调整操作的结果被添加到时钟信号或多个时钟信号的数据信号被改变。

3. 发明申请

US20090207850A1 System and method for data packet transmission and reception 失效
标题翻译：数据包发送和接收的系统和方法
公开(公告)号：US20090207850A1
公开(公告)日：2009-08-20
申请号：US12385885
申请日：2009-04-22
申请人： Hidekazu Osano , Hiroshi Nakayama
发明人： Hidekazu Osano , Hiroshi Nakayama
IPC分类号： H04L12/56
CPC分类号： G06F13/387
摘要： A system transmits a data packet from a transmitting apparatus to a receiving apparatus. The receiving apparatus includes a receive buffer, and a size specifying information transmitting unit that transmits size specifying information to the transmitting apparatus. The transmitting apparatus includes a transmit buffer, a credit storage unit that stores, as a credit, a value corresponding to a total size of all data packets stored in the receive buffer, a credit adding unit that adds a credit to the stored credit on transmitting a data packet, a credit subtracting unit that specifies a size of a read-out data packet on receiving the size specifying information, subtracts a credit corresponding to the specified size from a stored credit, and a transmission controlling unit that controls data packet transmission based on a credit stored in the credit storage unit.
摘要翻译：系统将数据分组从发送装置发送到接收装置。接收装置包括接收缓冲器和向发送装置发送大小指定信息的大小指定信息发送单元。发送装置包括发送缓冲器，信用存储单元，作为信用存储对应于存储在接收缓冲器中的所有数据分组的总大小的值;信用增加单元，用于向所发送的存储信用增加信用数据分组，信用减除单元，其在接收到大小指定信息时指定读出数据分组的大小，从存储的积分中减去与规定大小相对应的信用，以及控制数据分组发送的发送控制部，存储在信用存储单元中的信用。

4. 发明申请

US20080046769A1 Information processing apparatus and control method therefor 有权
标题翻译：信息处理装置及其控制方法
公开(公告)号：US20080046769A1
公开(公告)日：2008-02-21
申请号：US11790260
申请日：2007-04-24
申请人： Hidekazu Osano , Hiroshi Nakayama
发明人： Hidekazu Osano , Hiroshi Nakayama
IPC分类号： G06F1/30
CPC分类号： G06F3/067 , G06F3/0605 , G06F11/2056 , G06F11/3485 , H04L7/0004
摘要： A mutual electrically connecting part mutually connects a plurality of information processing parts, wherein the mutual connecting part comprises a phase adjusting part configured to adjust a phase from each of the respective ones of the plurality of information processing parts; and the mutual connecting part further has a power supply cut signal transmitting part transmitting a power supply cut signal, indicating that power supply to any one of the plurality of information processing parts is cut, to the phase adjusting part corresponding to the information processing part; and an initializing part initializing the phase adjusting part corresponding to the information proceeding part for which power supply is cut, in response to the transmission of the power supply cut signal from the power supply cut signal transmitting part.
摘要翻译：相互电连接部分相互连接多个信息处理部分，其中相互连接部分包括被配置为调整来自多个信息处理部分中的相应信息处理部分的相位的相位调整部分; 所述相互连接部还具有将与所述信息处理部对应的所述相位调整部发送指示向所述多个信息处理部中的任一个切断电力的供电切断信号的供电切断信号发送部，以及初始化部分，响应于来自电源切断信号发送部分的电源切断信号的传输，初始化对应于切断电源的信息进行部分的相位调整部分。

5. 发明申请

US20120239996A1 MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING MEMORY CONTROLLER 审中-公开
标题翻译：存储器控制器，信息处理装置和控制存储器控制器的方法
公开(公告)号：US20120239996A1
公开(公告)日：2012-09-20
申请号：US13402284
申请日：2012-02-22
申请人： Masanori HIGETA , Hiroshi Nakayama , Hidekazu Osano , Hideyuki Sakamaki , Kazuya Takaku
发明人： Masanori HIGETA , Hiroshi Nakayama , Hidekazu Osano , Hideyuki Sakamaki , Kazuya Takaku
IPC分类号： G06F11/07
CPC分类号： G06F11/1048
摘要： A memory controller which is connected to a memory module having an ECC (Error Check and Correction) function and which controls access to the memory module, the memory controller, has an error detection unit configured to detect an error bit and a position of the error bit by reading, from the memory module, information on codes of the ECCs corresponding to a plurality of read data read from the memory module, a buffer configured to temporarily store the plurality of read data, and a determination unit configured to determine, when the plurality of read data stored in the buffer include a number of data in which a correctable error is detected by the error detection unit and error detection positions of the detected data are the same as each other, that a correctable error is included in a group of the plurality of read data.
摘要翻译：连接到具有ECC（错误检查和校正）功能并且控制对存储器模块的访问的存储器模块的存储器控制器，存储器控制器具有错误检测单元，其被配置为检测错误位和错误的位置通过从存储器模块读取与从存储器模块读取的多个读取数据相对应的ECC的代码的信息，配置为临时存储多个读取数据的缓冲器，以及确定单元，存储在缓冲器中的多个读取数据包括由错误检测单元检测到可校正错误的数据的数量，并且检测到的数据的错误检测位置彼此相同，可纠正错误被包括在一组多个读取数据。

6. 发明授权

US07814356B2 Apparatus and control method for initializing a phase adjusting part in response to a power supply cut signal 有权
标题翻译：响应于电源切断信号初始化相位调整部件的装置和控制方法
公开(公告)号：US07814356B2
公开(公告)日：2010-10-12
申请号：US11790260
申请日：2007-04-24
申请人： Hidekazu Osano , Hiroshi Nakayama
发明人： Hidekazu Osano , Hiroshi Nakayama
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F1/12 , G06F1/24 , H04L7/00
CPC分类号： G06F3/067 , G06F3/0605 , G06F11/2056 , G06F11/3485 , H04L7/0004
摘要： A mutual electrically connecting part mutually connects a plurality of information processing parts, wherein the mutual connecting part comprises a phase adjusting part configured to adjust a phase from each of the respective ones of the plurality of information processing parts; and the mutual connecting part further has a power supply cut signal transmitting part transmitting a power supply cut signal, indicating that power supply to any one of the plurality of information processing parts is cut, to the phase adjusting part corresponding to the information processing part; and an initializing part initializing the phase adjusting part corresponding to the information proceeding part for which power supply is cut, in response to the transmission of the power supply cut signal from the power supply cut signal transmitting part.
摘要翻译：相互电连接部分相互连接多个信息处理部分，其中相互连接部分包括被配置为调整来自多个信息处理部分中的相应信息处理部分的相位的相位调整部分; 所述相互连接部还具有将与所述信息处理部对应的所述相位调整部发送指示向所述多个信息处理部中的任一个切断电力的供电切断信号的供电切断信号发送部，以及初始化部分，响应于来自电源切断信号发送部分的电源切断信号的传输，初始化对应于切断电源的信息进行部分的相位调整部分。

7. 发明申请

US20080175343A1 Phase adjusting function evaluating method, transmission margin measuring method, information processing apparatus, program and computer readable information recording medium 有权
标题翻译：相位调整功能评估方法，传输边缘测量方法，信息处理装置，程序和计算机可读信息记录介质
公开(公告)号：US20080175343A1
公开(公告)日：2008-07-24
申请号：US11987282
申请日：2007-11-28
申请人： Hiroshi Nakayama , Hidekazu Osano
发明人： Hiroshi Nakayama , Hidekazu Osano
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , H03K5/135 , H03L7/07 , H03L7/0812 , H04L7/0008 , H04L7/0037 , H04L7/0041 , H04L7/02
摘要： A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting operation is stored when the phase amount added to the clock signal or the plurality of data signals is changed.
摘要翻译：在接收装置中添加到时钟信号或用于调整其相位关系的多个数据信号的相位量被改变，并且当相位调整操作的结果被添加到时钟信号或多个时钟信号的数据信号被改变。

8. 发明授权

US08234428B2 Arbitration device that arbitrates conflicts caused in data transfers 失效
标题翻译：仲裁数据传输引起冲突的仲裁设备
公开(公告)号：US08234428B2
公开(公告)日：2012-07-31
申请号：US13190906
申请日：2011-07-26
申请人： Hidekazu Osano , Takayuki Kinoshita , Yoshikazu Iwami , Makoto Hataida
发明人： Hidekazu Osano , Takayuki Kinoshita , Yoshikazu Iwami , Makoto Hataida
IPC分类号： G06F13/368
CPC分类号： G06F13/36
摘要： An arbitration device including: a first measuring circuit to measure a first period; a second measuring circuit to measure a second period; a second selection circuit to select and output the first period or the second period according to a first selection signal; a first control circuit to output the first selection signal according to the first period and the second period; a third selection circuit to select a third data or either the first data or the second data according to a second selection signal; a third measuring circuit to measure a third period; a fourth measuring circuit to measure a fourth period; and a second control circuit to output the second selection signal according to either the selected first period or the selected second period and the third period and the fourth period.
摘要翻译：一种仲裁装置，包括：第一测量电路，用于测量第一周期; 用于测量第二周期的第二测量电路; 第二选择电路，用于根据第一选择信号选择和输出第一周期或第二周期; 第一控制电路，用于根据第一周期和第二周期输出第一选择信号; 第三选择电路，用于根据第二选择信号选择第三数据或第一数据或第二数据; 测量第三周期的第三测量电路; 测量第四周期的第四测量电路; 以及第二控制电路，用于根据所选择的第一周期或所选择的第二周期以及第三周期和第四周期输出第二选择信号。

9. 发明授权

US08539127B2 Linkup state generating method, information processing apparatus, and linkup state generating program 失效
标题翻译：链接状态生成方法，信息处理装置和链接状态生成程序
公开(公告)号：US08539127B2
公开(公告)日：2013-09-17
申请号：US12630430
申请日：2009-12-03
申请人： Yoshikazu Iwami , Hidekazu Osano , Takayuki Kinoshita
发明人： Yoshikazu Iwami , Hidekazu Osano , Takayuki Kinoshita
IPC分类号： G06F13/10
CPC分类号： G06F13/102 , G06F11/3636
摘要： A linkup state generating method for generating a state in which linkup is completed in first and second information processing apparatuses, the first and second information processing apparatuses each including a linkup function of, with parameter exchange, comparing parameters included in the first and second information processing apparatuses and adjusting specifications of the parameters so that the specifications of the parameters match each other, the linkup state generating method including setting, from the outside, a parameter in the first information processing apparatus so that a specification of the parameter included in the first information processing apparatus matches a specification of a parameter included in the second information processing apparatus, and sending, from the first information processing apparatus, a signal received from the second information processing apparatus to the second information processing apparatus in a manner that the second information processing apparatus recognizes that parameter exchange has been performed.
摘要翻译：一种链接状态生成方法，用于生成在第一和第二信息处理设备中完成连接的状态，第一和第二信息处理设备各自包括具有参数交换的连接功能，比较包括在第一和第二信息处理中的参数装置和调整参数的规格，使得参数的规格彼此匹配，所述链接状态生成方法包括从外部设置第一信息处理装置中的参数，使得包括在第一信息中的参数的规范处理装置将包括在第二信息处理装置中的参数的规格进行匹配，并且以第二信息处理方式从第一信息处理装置发送从第二信息处理装置接收到的信号到第二信息处理装置基本设备认识到已经执行了参数交换。

10. 发明申请

US20060209820A1 Cross bar apparatus, and method and program for controlling the same 失效
标题翻译：横杆装置及其控制方法和程序
公开(公告)号：US20060209820A1
公开(公告)日：2006-09-21
申请号：US11181826
申请日：2005-07-15
申请人： Hideto Arai , Nobuyuki Suzuki , Hidekazu Osano , Shu Nakamura
发明人： Hideto Arai , Nobuyuki Suzuki , Hidekazu Osano , Shu Nakamura
IPC分类号： H04L12/56 , H04L12/54
CPC分类号： G06F15/17375
摘要： The frequency of the internal clock is set at ½ of the frequency of an external clock as well as the width of the internal bus is configured to be twice as wide as the width of an external bus. A write control unit controls a bypass unit and a swap circuit unit and, when a plurality of packets are received, writes words of the packets such that headers H of the received packets are respectively arranged alternately in each packet storage sector between an even-numbered queue and an odd-numbered queue. A read control unit reads the words of the packets in parallel by two words at each time from the even-numbered queue and the odd-numbered queue.
摘要翻译：内部时钟的频率设置为外部时钟频率的1/2，内部总线的宽度被设置为外部总线宽度的两倍。写控制单元控制旁路单元和交换电路单元，并且当接收到多个分组时，写入分组的字，使得接收到的分组的报头H分别交替地布置在偶数编号的每个分组存储扇区中队列和奇数队列。读取控制单元从偶数队列和奇数队列在每次从并行读取两个字的分组的字。

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