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1. 发明授权

US07110279B2 Memory 有权
标题翻译：记忆
公开(公告)号：US07110279B2
公开(公告)日：2006-09-19
申请号：US10935554
申请日：2004-09-08
申请人： Hideaki Miyamoto , Yoshiyuki Ishizuka , Naofumi Sakai
发明人： Hideaki Miyamoto , Yoshiyuki Ishizuka , Naofumi Sakai
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： A memory capable of suppressing disturbance is provided. This memory activates each of a selected word line and a bit line corresponding to unrewritten storage means while keeping potential difference therebetween at a level not more than a prescribed value and differentiates the length of a period for applying a voltage for rewriting to each of the selected word line and a bit line corresponding to rewritten storage means from the length of a transition period of the potential of at least either the word line or the bit line corresponding to the unrewritten storage means when performing a rewrite operation on partial selected storage means or performing no rewrite operation on all selected storage means.
摘要翻译：提供了能够抑制干扰的存储器。该存储器激活对应于未启动存储装置的选定字线和位线中的每一个，同时保持它们之间的电位差不超过规定值，并且将用于重写的电压的周期长度区分为所选择的每一个字线和对应于重写存储装置的位线，当对部分选择的存储装置执行重写操作时，从对应于未刷新存储装置的字线或位线中的至少一个的电位的转变周期的长度的长度，对所有选定的存储装置不进行重写操作。

2. 发明申请

US20050052914A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20050052914A1
公开(公告)日：2005-03-10
申请号：US10932081
申请日：2004-09-02
申请人： Hideaki Miyamoto , Naofumi Sakai , Yoshiyuki Ishizuka
发明人： Hideaki Miyamoto , Naofumi Sakai , Yoshiyuki Ishizuka
IPC分类号： H01L27/10 , G11C5/02 , G11C11/00 , G11C11/22 , H01L21/8246 , H01L27/105
CPC分类号： G11C5/025 , G11C11/22
摘要： A semiconductor memory device allowing miniaturization is provided. This semiconductor memory device comprises a word line and a bit line arranged to intersect with each other, a memory cell array region including a plurality of memory cells connected to the word line and the bit line and a transfer gate transistor arranged under the memory cell array region.
摘要翻译：提供允许小型化的半导体存储器件。这种半导体存储器件包括一个字线和位线相互交叉排列，一个存储单元阵列区域包括连接到该字线和该位线的多个存储单元，以及一个布置在该存储单元阵列下面的一个传输门晶体管地区。

3. 发明申请

US20050057958A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20050057958A1
公开(公告)日：2005-03-17
申请号：US10935554
申请日：2004-09-08
申请人： Hideaki Miyamoto , Yoshiyuki Ishizuka , Naofumi Sakai
发明人： Hideaki Miyamoto , Yoshiyuki Ishizuka , Naofumi Sakai
IPC分类号： G11C16/12 , G11C11/22 , G11C16/24
CPC分类号： G11C11/22
摘要： A memory capable of suppressing disturbance is provided. This memory activates each of a selected word line and a bit line corresponding to unrewritten storage means while keeping potential difference therebetween at a level not more than a prescribed value and differentiates the length of a period for applying a voltage for rewriting to each of the selected word line and a bit line corresponding to rewritten storage means from the length of a transition period of the potential of at least either the word line or the bit line corresponding to the unrewritten storage means when performing a rewrite operation on partial selected storage means or performing no rewrite operation on all selected storage means.
摘要翻译：提供了能够抑制干扰的存储器。该存储器激活对应于未启动存储装置的所选字线和位线中的每一个，同时保持它们之间的电位差不超过规定值，并且将用于重写的电压的周期长度区分为所选择的每一个字线和对应于重写存储装置的位线，当对部分选择的存储装置执行重写操作时，从对应于未刷新存储装置的字线或位线中的至少一个的电位的转变周期的长度的长度，对所有选定的存储装置不进行重写操作。

4. 发明申请

US20070237016A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20070237016A1
公开(公告)日：2007-10-11
申请号：US11630851
申请日：2005-06-16
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C7/00
CPC分类号： G11C11/22
摘要： A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell(12). During this access operation, it is performed to apply to the memory cell(12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell(12).
摘要翻译：可以抑制其中未选择的存储单元中的数据丢失的任何“干扰效应”的存储器。该存储器具有存储单元阵列（1），该存储单元阵列（1）包括位线，设置成与位线相交的字线以及每个连接在位线和字线之间的存储单元（12）。在该存储器中，对选择的存储器单元（12）进行包括读取，重写和写入操作中的至少一个的访问操作。在该访问操作期间，执行向存储器单元（12）施加第一电压脉冲，该第一电压脉冲在第一方向上提供电场以反转存储的数据，以及第二电压脉冲，其提供为电场与第一个方向相反的方向，以便不反转存储的数据。此外，对存储单元（12）进行用于恢复残留极化量的恢复操作。

5. 发明授权

US07652908B2 Ferroelectric memory having a refresh control circuit capable of recovering residual polarization of unselected memory cells 有权
标题翻译：铁电存储器具有能够恢复未选择的存储单元的剩余极化的刷新控制电路
公开(公告)号：US07652908B2
公开(公告)日：2010-01-26
申请号：US11630851
申请日：2005-06-16
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array (1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells (12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell (12). During this access operation, it is performed to apply to the memory cell (12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell (12).
摘要翻译：可以抑制其中未选择的存储单元中的数据丢失的任何“干扰效应”的存储器。该存储器具有存储单元阵列（1），该存储单元阵列（1）包括位线，设置成与位线相交的字线以及各自连接在位线和字线之间的存储单元（12）。在该存储器中，对选择的存储器单元（12）进行包括读取，重写和写入操作中的至少一个的访问操作。在该访问操作期间，执行向存储器单元（12）施加第一电压脉冲，该第一电压脉冲在第一方向上提供电场以反转存储的数据，以及第二电压脉冲，其提供为电场与第一个方向相反的方向，以便不反转存储的数据。此外，对存储单元（12）进行用于恢复残留极化量的恢复操作。

6. 发明授权

US07366004B2 Memory 有权
标题翻译：记忆
公开(公告)号：US07366004B2
公开(公告)日：2008-04-29
申请号：US11328223
申请日：2006-01-10
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.
摘要翻译：提供了能够抑制数据读取中的读取电压的降低而不管制造过程中的分散性的存储器。该存储器包括电荷存储装置，第一场效应晶体管和数据确定装置。存储器将第一场效应晶体管的控制端子和剩余的第一端子之间的电压设置为阈值电压，以使第一场效应晶体管处于ON和OFF之间的边界状态附近的截止状态 - 通过第一场效应晶体管的阈值电压。

7. 发明申请

US20060164877A1 Memory 有权
标题翻译：记忆
公开(公告)号：US20060164877A1
公开(公告)日：2006-07-27
申请号：US11328223
申请日：2006-01-10
申请人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
发明人： Hideaki Miyamoto , Naofumi Sakai , Kouichi Yamada , Shigeharu Matsushita
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.
摘要翻译：提供了能够抑制数据读取中的读取电压的降低而不管制造过程中的分散性的存储器。该存储器包括电荷存储装置，第一场效应晶体管和数据确定装置。存储器将第一场效应晶体管的控制端子和剩余的第一端子之间的电压设置为阈值电压，以使第一场效应晶体管处于ON和OFF之间的边界状态附近的截止状态 - 通过第一场效应晶体管的阈值电压。

8. 发明授权

US08983122B2 Image processing apparatus, image processing method, and computer-readable storage medium 有权
标题翻译：图像处理装置，图像处理方法和计算机可读存储介质
公开(公告)号：US08983122B2
公开(公告)日：2015-03-17
申请号：US13411445
申请日：2012-03-02
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G06K9/00 , G06T5/00
CPC分类号： G06T5/007 , G06T5/002 , G06T2207/10116 , G06T2207/20004 , G06T2207/20021
摘要： An image processing apparatus includes a first acquisition unit configured to obtain identification information for a plurality of blocks of an image, a second acquisition unit configured to obtain information to be used for image processing from a pixel value of a region of the image determined based on the identification information, and an image processing unit configured to perform image processing of the image based on the information obtained by the second acquisition unit.
摘要翻译：一种图像处理装置包括：第一获取单元，被配置为获得图像的多个块的识别信息;第二获取单元，被配置为从根据图像确定的图像的区域的像素值获得用于图像处理的信息所述识别信息和图像处理单元，被配置为基于由所述第二获取单元获得的信息来执行所述图像的图像处理。

9. 发明授权

US08805041B2 X-ray image processing apparatus, X-ray image processing method, and storage medium for computer program 有权
标题翻译： X射线图像处理装置，X射线图像处理方法以及计算机程序的存储介质
公开(公告)号：US08805041B2
公开(公告)日：2014-08-12
申请号：US13515677
申请日：2010-12-10
申请人： Hideaki Miyamoto
发明人： Hideaki Miyamoto
IPC分类号： G06K9/00
CPC分类号： G06T5/009 , A61B6/481 , A61B6/486 , A61B6/504 , G06T5/50 , G06T7/13 , G06T2207/10016 , G06T2207/10121 , G06T2207/20192 , G06T2207/20224 , G06T2207/30101 , G06T2207/30104
摘要： A feature value is extracted from a boundary region that is located between a contrast-agent injection region and a background region in a subtraction image, a gradation curve depending on the feature value is generated, and gradation processing is performed by applying the gradation curve to the subtraction image.
摘要翻译：从减法图像中的造影剂注入区域和背景区域之间的边界区域提取特征值，生成根据特征值的灰度曲线，并且通过将灰度曲线应用于减法图像。

10. 发明授权

US08710446B2 Imaging apparatus, control method thereof, and program 有权
标题翻译：成像设备及其控制方法及程序
公开(公告)号：US08710446B2
公开(公告)日：2014-04-29
申请号：US12765108
申请日：2010-04-22
申请人： Hitoshi Inoue , Hideaki Miyamoto , Hiroyuki Omi
发明人： Hitoshi Inoue , Hideaki Miyamoto , Hiroyuki Omi
IPC分类号： G01T1/24 , G01D18/00 , G06K9/00 , G01N23/04 , H05G1/64
CPC分类号： G01T1/2928
摘要： An imaging apparatus includes: a plurality of photoelectric converters each adapted to perform photoelectric conversion in response to receiving light, and output an electrical signal; a holding unit adapted to hold, for each of the plurality of photoelectric converters, a correction value for correcting photoelectric conversion characteristics of the photoelectric converter; and a correction unit adapted to correct each of the electrical signals output by the plurality of photoelectric converters, using the corresponding correction values, wherein the correction unit corrects each of the electrical signals based on the correction values, which have been increased or decreased in accordance with a prescribed pixel arrangement pattern, and the imaging apparatus comprises a determination unit adapted to evaluate correction results that are based on the correction values increased or decreased in accordance with the prescribed pattern, and determine a presence of a correction error in the correction values held in the holding unit.
摘要翻译：一种成像装置包括：多个光电转换器，每个光电转换器适于响应于接收光执行光电转换，并输出电信号; 保持单元，适于为所述多个光电转换器中的每一个保持用于校正所述光电转换器的光电转换特性的校正值; 以及校正单元，其使用相应的校正值来校正由所述多个光电转换器输出的每个电信号，其中所述校正单元基于已经根据所述多个光电转换器增大或减小的校正值校正每个所述电信号具有规定的像素排列图案，并且所述成像装置包括确定单元，所述确定单元适于基于根据所述规定图案增加或减少的校正值来评估校正结果，并且确定所保持的校正值中存在校正误差在持有单位。

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