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    • 3. 发明授权
    • Method and apparatus for blockwise storage of pictures having variable
aspect ratios
    • 用于具有可变宽度比例的图像的块状存储的方法和装置
    • US5239512A
    • 1993-08-24
    • US649518
    • 1991-01-31
    • Thierry FautierJean-Pierre Michel
    • Thierry FautierJean-Pierre Michel
    • G06F12/02G06T1/60
    • G06T1/60G06F12/0207
    • In this method, the pictures are processed in blocks whose dimensions (H,V) expressed in a number of pixels are integral powers of two, and the contents (pixels) of the different blocks are stored in the memories one after the other. The device for calculating the position of a pixel in the memory from the position x, y of the said pixel in the picture is formed by two material operators 11, 12 which extract from x and y, respectively, the most significant bits m and p, m and p being the integers such as 2.sup.m =H and 2.sup.p 32 V, a multiplier 19 multiplying the number of blocks in a picture line NBLOCH by the vertical component ADBLOCV supplied by the operator 12, and an adder 20 which adds together the result supplied by the said multiplier and the coordinate ADBLOCH supplied by the operator 11.
    • 在这种方法中,在以像素数表示的维度(H,V)为2的积分功率的块中处理图像,并且将不同块的内容(像素)一个接一个地存储在存储器中。 用于从图像中的所述像素的位置x,y计算存储器中的像素的位置的装置由分别从x和y提取最高有效位m和p的两个素材算符11,12形成 ,m和p是诸如2m = H和2p32V的整数,乘法器19将图像行NBLOCH中的块数乘以由运算器12提供的垂直分量ADBLOCV和将所提供的结果相加的加法器20 由所述乘法器和由操作器11提供的坐标ADBLOCH。
    • 5. 发明授权
    • Integrated D/A converter including means for reducing glitches
    • 集成D / A转换器包括减少毛刺的装置
    • US4918447A
    • 1990-04-17
    • US860270
    • 1986-05-06
    • Jean-Pierre Michel
    • Jean-Pierre Michel
    • H03M1/08H03M1/00
    • H03M1/0863H03M1/745
    • An integrated digital-to-analogue (D/A) converter circuit provided with a device for reducing glitches. The D/A converter converts control signals having n binary states Bn into analogue signals and comprises n differential pairs Pn of transistors T1n and T2n connected to n current generators which supply currents of a value In weighted according to the binary weights 2.sup.n of the binary states Bn. The transistors T1n receives their respective binary control signals and the transistors T2n receive the respective binary control signals inverse to the preceding signals. The triggering instant of the differential pairs at a leading edge of the control signal is shifted over the triggering instant at a leading edge of the control signal in that a shift of the triggering thresholds of the transistors T1n with respect to the transistors T2n is effected over a constant value Vd obtained by the device for reducing glitches and constituted by resistors Rn connected in series with the emitters of the transistors of one of the series of transistors T1n or T2n in such a manner that Rn..sup.In/.sub.2 =Vd.
    • 一种集成的数模(D / A)转换器电路,其具有用于减少毛刺的装置。 D / A转换器将具有n个二进制状态Bn的控制信号转换为模拟信号,并且包括连接到n个电流发生器的晶体管T1n和T2n的n个差分对Pn,其提供根据二进制状态的二进制权重2n加权的值In的电流 Bn。 晶体管T1n接收它们各自的二进制控制信号,并且晶体管T2n接收与先前信号相反的相应的二进制控制信号。 在控制信号的前沿的触发时刻,在控制信号的前沿的差分对的触发时刻在晶体管T1n的触发阈值相对于晶体管T2n的移动是在 通过用于减少毛刺并由与串联晶体管T1n或T2n中的一个晶体管的晶体管的发射极串联连接的电阻器Rn构成的器件获得的恒定值Vd以使得Rn.In/2=Vd。
    • 7. 发明授权
    • Arrangement for deciphering and decoding television pictures encoded in
accordance with the MAC standard and scrambled at transmission by
submitting the video signals to cyclic permutations
    • 用于解密和解码根据MAC标准编码的电视图像并通过将视频信号提交到循环排列而在发送时加扰的装置
    • US4691352A
    • 1987-09-01
    • US711545
    • 1985-03-13
    • Jean-Pierre ArragonJean-Pierre Michel
    • Jean-Pierre ArragonJean-Pierre Michel
    • H04K1/06H03M7/30H04B7/15H04K1/00H04N7/169H04N11/00H04N11/24H04N7/167
    • H04N7/1696
    • An arrangement for deciphering and decoding television pictures which were scrambled at transmission by submitting the video signals to cyclic permutations from the addresses x.sub.i of points of cut produced by a pseudo-random digital address generator. Said video signals being separate components such as analog components of the MAC type, the arrangement comprises for recreating the permuted signals two sets of random access memories (Y.sub.1, Y.sub.2) and (C.sub.1, C.sub.2, C.sub.3, C.sub.4) which are used alternately, and deciphering and decoding are realized for each component either by a first phase in which the memory is written obtained by an address jump as a function of the address of said points of cut followed by a second phase in which the memory is read sequentially, which in addition provides the time expansion of the compressed signals, or by a first phase in which the memory is written sequentially followed by a second memory read phase obtained by address jumps as a function of the address of said point of cut and which ensures in addition the time expansion of the compressed signals.
    • 通过从由伪随机数字地址发生器产生的切割点的地址xi将视频信号提交到循环排列来解密和解码电视图像的装置。 所述视频信号是诸如MAC类型的模拟分量的分离组件,该装置包括用于重新创建交替使用的两组随机存取存储器(Y1,Y2)和(C1,C2,C3,C4)两组, 对于每个组件,通过第一阶段来实现对每个组件的解密和解码,第一阶段是通过地址跳转获得的存储器作为所述切割点的地址的函数,其次是顺序地读取存储器的第二阶段的函数, 另外还提​​供压缩信号的时间扩展,或通过顺序写入存储器的第一阶段,随后是通过作为所述切割点的地址的函数的地址跳跃获得的第二存储器读取相位,并且另外确保 压缩信号的时间扩展。