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1. 发明申请

US20050044305A1 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US20050044305A1
公开(公告)日：2005-02-24
申请号：US10887019
申请日：2004-07-08
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G06F12/00 , G06F13/16 , G11C5/06 , G11C7/10 , G11C11/41
CPC分类号： G11C5/063
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.
摘要翻译：本发明涉及一种半导体存储器模块，其具有布置在至少一行的多个存储器芯片和至少一个缓冲器芯片，该缓冲器芯片驱动并接收时钟信号，以及将命令和寻址信号存储到存储器芯片以及从存储器芯片传送数据信号通过模块内的时钟，地址，命令和数据总线，并形成与外部主存储器总线的接口。半导体存储器模块具有布置在其上的偶数个缓冲器芯片，并且所有存储器芯片至少通过一个信号线类型从信号组连接到两个相应的缓冲器芯片，并且仅剩下两个缓冲器芯片之一来自该组的信号线。在读取操作期间，通过其线从一个缓冲芯片到相应的一个存储器芯片的致动信号的电信号传播时间和从该存储器芯片到另一个缓冲器芯片的数据信号的电信号传播时间之和对于所有存储器芯片是相同的，并且提供用于控制到存储器芯片或从存储器芯片的相应数据写入和读取操作的控制装置，以便以与数据相同的相同方向驱动时钟信号和命令和寻址信号当数据被写入和读取时通过模块内的总线发送信号。

2. 发明授权

US07061784B2 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US07061784B2
公开(公告)日：2006-06-13
申请号：US10886814
申请日：2004-07-08
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G11C5/06
CPC分类号： G11C11/4093 , G11C5/063 , G11C7/10
摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.
摘要翻译：本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们时钟，地址，命令和数据总线。缓冲芯片形成与外部存储器主总线的接口。数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。

3. 发明授权

US07386696B2 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US07386696B2
公开(公告)日：2008-06-10
申请号：US10887019
申请日：2004-07-08
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G06F12/00
CPC分类号： G11C5/063
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.
摘要翻译：本发明涉及一种半导体存储器模块，其具有布置在至少一行的多个存储器芯片和至少一个缓冲器芯片，该缓冲器芯片驱动并接收时钟信号，以及将命令和寻址信号存储到存储器芯片以及从存储器芯片传送数据信号通过模块内的时钟，地址，命令和数据总线，并形成与外部主存储器总线的接口。半导体存储器模块具有布置在其上的偶数个缓冲器芯片，并且所有存储器芯片至少通过一个信号线类型从信号组连接到两个相应的缓冲器芯片，并且仅剩下两个缓冲器芯片之一来自该组的信号线。在读取操作期间，通过其线从一个缓冲芯片到相应的一个存储器芯片的致动信号的电信号传播时间和从该存储器芯片到另一个缓冲器芯片的数据信号的电信号传播时间之和对于所有存储器芯片是相同的，并且提供用于控制到存储器芯片或从存储器芯片的相应数据写入和读取操作的控制装置，以便以与数据相同的相同方向驱动时钟信号和命令和寻址信号当数据被写入和读取时通过模块内的总线发送信号。

4. 发明授权

US07224636B2 Semiconductor memory module 有权
标题翻译：半导体存储器模块
公开(公告)号：US07224636B2
公开(公告)日：2007-05-29
申请号：US10890934
申请日：2004-07-14
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G11C8/00
CPC分类号： G11C29/028 , G11C5/063 , G11C29/50012
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.
摘要翻译：本发明涉及一种半导体存储器模块，该半导体存储器模块具有彼此排成一列的多个存储器芯片。存储器模块具有模块内部时钟，命令/地址和数据总线，其将时钟信号，命令和地址信号以及数据信号从存储器控制器设备传送到存储器芯片，并将数据信号从存储器芯片传送到存储器控制器设备。存储器模块具有各自的时钟，命令/地址和数据信号线。时钟信号线包括两个差分时钟信号线，它们在其与存储器控制器装置相对的端部通过短路桥断开或彼此连接。在写入操作期间，存储器芯片将写入数据与从存储器控制器设备运行到时钟信号线的时钟信号同步，并且在读取操作期间，与从该存储器控制器设备反射的时钟信号同步地输出读取数据开路或短路的时钟信号线。

5. 发明授权

US06972981B2 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US06972981B2
公开(公告)日：2005-12-06
申请号：US10909205
申请日：2004-07-30
申请人： Hermann Ruckerbauer , Maksim Kuzmenka , Andreas Jakobs
发明人： Hermann Ruckerbauer , Maksim Kuzmenka , Andreas Jakobs
IPC分类号： G11C5/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C7/222 , G11C5/063 , G11C7/22 , G11C11/4076
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row. The memory chips have separate writing and reading clock signal inputs for receiving the clock signals and the clock signal lines are routed in at least one loop, via the memory chips, from the buffer chip to the end of each row and from there back to the buffer chip
摘要翻译：本发明涉及具有多个存储器芯片和至少一个缓冲芯片的半导体存储器模块，其驱动时钟信号并将命令和寻址信号传送到存储器芯片，并且还将数据信号驱动至存储器芯片并从存储器芯片接收它们，并经由模块内部时钟，地址，命令和数据信号总线。缓冲芯片形成与外部存储器主总线的接口，并且存储器芯片布置在至少一行中。存储器芯片具有单独的写入和读取时钟信号输入，用于接收时钟信号，并且时钟信号线在至少一个循环中经由存储器芯片从缓冲器芯片路由到每行的末端，并且从那里返回到缓冲芯片

6. 发明申请

US20050078532A1 Semiconductor memory module 失效
公开(公告)号：US20050078532A1
公开(公告)日：2005-04-14
申请号：US10909205
申请日：2004-07-30
申请人： Hermann Ruckerbauer , Maksim Kuzmenka , Andreas Jakobs
发明人： Hermann Ruckerbauer , Maksim Kuzmenka , Andreas Jakobs
IPC分类号： G11C5/06 , G11C7/22 , G11C11/4076 , G11C7/00
CPC分类号： G11C7/222 , G11C5/063 , G11C7/22 , G11C11/4076
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row. The memory chips have separate writing and reading clock signal inputs for receiving the clock signals and the clock signal lines are routed in at least one loop, via the memory chips, from the buffer chip to the end of each row and from there back to the buffer chip

7. 发明申请

US20050036349A1 Semiconductor memory module 有权
标题翻译：半导体存储器模块
公开(公告)号：US20050036349A1
公开(公告)日：2005-02-17
申请号：US10890934
申请日：2004-07-14
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C29/028 , G11C5/063 , G11C29/50012
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.
摘要翻译：本发明涉及一种半导体存储器模块，该半导体存储器模块具有彼此排成一列的多个存储器芯片。存储器模块具有模块内部时钟，命令/地址和数据总线，其将时钟信号，命令和地址信号以及数据信号从存储器控制器设备传送到存储器芯片，并将数据信号从存储器芯片传送到存储器控制器设备。存储器模块具有各自的时钟，命令/地址和数据信号线。时钟信号线包括两个差分时钟信号线，它们在其与存储器控制器装置相对的端部通过短路桥断开或彼此连接。在写入操作期间，存储器芯片将写入数据与从存储器控制器设备运行到时钟信号线的时钟信号同步，并且在读取操作期间，与从该存储器控制器设备反射的时钟信号同步地输出读取数据开路或短路的时钟信号线。

8. 发明申请

US20050024963A1 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US20050024963A1
公开(公告)日：2005-02-03
申请号：US10886814
申请日：2004-07-08
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G11C5/06 , G11C7/10 , G11C11/4093 , G11C7/00
CPC分类号： G11C11/4093 , G11C5/063 , G11C7/10
摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.
摘要翻译：本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们时钟，地址，命令和数据总线。缓冲芯片形成与外部存储器主总线的接口。数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。

9. 发明申请

US20060227627A1 Buffer component for a memory module, and a memory module and a memory system having such buffer component 有权
标题翻译：用于存储器模块的缓冲器组件，以及具有这种缓冲器组件的存储器模块和存储器系统
公开(公告)号：US20060227627A1
公开(公告)日：2006-10-12
申请号：US11368267
申请日：2006-03-03
申请人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
发明人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
IPC分类号： G11C7/10
CPC分类号： G11C5/063 , G06F13/1689 , G11C5/04 , G11C7/1078 , G11C7/109
摘要： The invention relates to a buffer component for a memory module having a plurality of memory components, comprising a first data interface for receiving an item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeeding second clock period of the clock signal, whereby the address and command signals present are accepted into the group of the plurality of memory components.
摘要翻译：本发明涉及一种用于具有多个存储器组件的存储器模块的缓冲器组件，包括：第一数据接口，用于根据数据传输协议接收访问信息项，地址，时钟，控制和命令信号取决于访问信息，用于驱动时钟信号的第二数据接口，以及对多个存储器组件的地址和命令信号，以及根据信令协议将控制信号驱动到多组存储器组件的一组，其中激活存储器组件和地址和命令信号的接受以取决于控制信号的方式实现;以及控制单元，其在时钟信号的第一时钟周期期间将地址和命令信号施加到多个存储器组件并应用所述控制信号用于将所述多个存储器组件的组激活到所述多个组中的组在时钟信号的随后的第二时钟周期中存在地址和命令信号时被激活的多路分量，由此存在的地址和命令信号被接收到多个存储器组件的组中。

10. 发明申请

US20060197566A1 DLL circuit for providing an output signal with a desired phase shift 审中-公开
标题翻译： DLL电路，用于提供具有所需相移的输出信号
公开(公告)号：US20060197566A1
公开(公告)日：2006-09-07
申请号：US11358940
申请日：2006-02-21
申请人： Andreas Jakobs , Andreas Taeuber
发明人： Andreas Jakobs , Andreas Taeuber
IPC分类号： H03L7/06
CPC分类号： H03K5/131
摘要： The present invention relates to a DLL circuit for providing an output signal which is shifted with by a desired phase shift with respect to a periodic input signal. In one embodiment, the DLL Circuit comprises a plurality of delay elements all having the same delay time and being connected in series to form a delay chain, wherein the periodic input signal is applied to the first delay element of the delay chain. The DLL circuit further comprises a detection unit which is connected to the outputs of at least a portion of the delay elements and which is provided to determine which delay element a particular edge of the periodic signal has reached after a predetermined phase progress of the periodic signal, and to generate a corresponding control information which indicates at which delay element the particular edge of the periodic signal has last been determined. The DLL circuit further comprises a selection circuit for selecting one of the delay elements depending on the control information and depending on the desired phase shift and outputting the signal at the output of the selected delay elements as the output signal of the DLL circuit.
摘要翻译：本发明涉及一种用于提供输出信号的DLL电路，该输出信号相对于周期性输入信号被移位期望的相移。在一个实施例中，DLL电路包括多个具有相同延迟时间并被串联连接以形成延迟链的延迟元件，其中周期性输入信号被施加到延迟链的第一延迟元件。 DLL电路还包括检测单元，其连接到延迟元件的至少一部分的输出，并且被提供用于确定在周期信号的预定相位进行之后周期信号的特定边缘已经到达的延迟元件并且产生相应的控制信息，该控制信息指示周期信号的特定边缘最后被确定在哪个延迟元件。 DLL电路还包括一个选择电路，用于根据控制信息选择一个延迟元件，并根据期望的相移，并输出所选延迟元件的输出端的信号作为DLL电路的输出信号。

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